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参数资料
| 型号： | MSC8103VT1100F |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 19/104页 |
| 文件大小： | 0K |
| 描述： | IC DSP 16BIT 275MHZ 332-FCPBGA |
| 标准包装： | 90 |
| 系列： | StarCore |
| 类型： | SC140 内核 |
| 接口： | 通信处理器模块（CPM） |
| 时钟速率： | 275MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 512kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.60V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 332-BFBGA，FCPBGA |
| 供应商设备封装： | 332-FCBGA（17x17） |
| 包装： | 托盘 |
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CPM Ports
MSC8103 Network Digital Signal Processor, Rev. 12
Freescale Semiconductor
1-17
PA27
FCC1: RXSOC
UTOPIA slave
FCC1: RX_DV
MII
Output
Input
FCC1: UTOPIA Receive Start of Cell
Asserted by the MSC8103 (UTOPIA slave) for an external PHY when
RXD[0–7] contains the first valid byte of the cell.
FCC1: Media Independent Interface Receive Data Valid
Asserted by an external fast Ethernet PHY to indicate that valid data is
being sent. The presence of carrier sense but not RX_DV indicates
reception of broken packet headers, probably due to bad wiring or a bad
circuit.
PA26
FCC1: RXCLAV
UTOPIA slave
FCC1: RXCLAV
UTOPIA master, or
RXCLAV0
UTOPIA master, Multi-PHY, direct
polling
FCC1: RX_ER
MII
Output
Input
FCC1: UTOPIA Slave Receive Cell Available
Asserted by the MSC8103 (UTOPIA slave PHY) when one complete
ATM cell is available for transfer.
FCC1: UTOPIA Master Receive Cell Available
Asserted by an external PHY when one complete ATM cell is available
for transfer.
FCC1: UTOPIA Master Receive Cell Available 0 Direct Polling
Asserted by an external PHY when one complete ATM cell is available
for transfer.
FCC1: Media Independent Interface Receive Error
Asserted by an external fast Ethernet PHY to indicate a receive error,
which often indicates bad wiring.
PA25
FCC1: TXD0
UTOPIA
SDMA: MSNUM0
Output
FCC1: UTOPIA Transmit Data Bit 0
The MSC8103 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
Module Serial Number Bit 0
The MSNUM has 6 bits that identify devices using the serial DMA
(SDMA) modules. MSNUM[0–4] is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates the section,
transmit (0) or receive (1), that is active during the transfer. The
information is recorded in the SDMA transfer error registers.
PA24
FCC1: TXD1
UTOPIA
SDMA: MSNUM1
Output
FCC1: UTOPIA Transmit Data Bit 1
The MSC8103 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. This is bit 1 of the transmit data. TXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes.
Module Serial Number Bit 1
The MSNUM has 6 bits that identify devices using the serial DMA
(SDMA) modules. MSNUM[0–4] is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates the section,
transmit (0) or receive (1), that is active during the transfer. The
information is recorded in the SDMA transfer error registers.
PA23
FCC1: TXD2
UTOPIA
Output
FCC1: UTOPIA Transmit Data Bit 2
The MSC8103 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. This is bit 2 of the transmit data. TXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes.
Table 1-7.
Port A Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated Signal
Protocol
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