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参数资料
型号： MSC8144ADS
厂商： Freescale Semiconductor
文件页数： 2/80页
文件大小： 0K
描述： ADS FOR MSC8144 DEVICE
标准包装： 1
类型： DSP
适用于相关产品： MSC8144
所含物品： AMC 卡、电源、缆线、USB TAP、硬件和说明文档
Table of Contents
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2
3
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7
Pin Assignments and Reset States. . . . . . . . . . . . . . . . . . . . . .4
1.1 FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .27
2.3 Default Output Driver Characteristics . . . . . . . . . . . . . .28
2.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .28
2.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .29
2.6 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .64
3.1 Start-up Sequencing Recommendations . . . . . . . . . . .64
3.2 Power Supply Design Considerations. . . . . . . . . . . . . .66
3.3 Clock and Timing Signal Board Layout Considerations 67
3.4 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .67
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Figure 12.Transmitter Output Compliance Mask . . . . . . . . . . . . . .
Figure 13.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . .
Figure 14.Receiver Input Compliance Mask . . . . . . . . . . . . . . . . .
Figure 15.PCI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 16.PCI Input AC Timing Measurement Conditions . . . . . . .
Figure 17.PCI Output AC Timing Measurement Condition . . . . . .
Figure 18.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 20.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 21.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 22.UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 23.Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 24.MII Management Interface Timing . . . . . . . . . . . . . . . . .
Figure 25.MII Transmit AC Timing . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 26.AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 27.MII Receive AC Timing . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 28.RMII Transmit and Receive AC Timing . . . . . . . . . . . . .
Figure 29.AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 30.SMII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . .
Figure 31.RGMII AC Timing and Multiplexing . . . . . . . . . . . . . . . .
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58
59
List of Figures
Figure 32.ATM/UTOPIA/POS AC Test Load . . . . . . . . . . . . . . . . .
Figure 33.ATM/UTOPIAPOS AC Timing (External Clock) . . . . . . .
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60
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
MSC8144 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
StarCore SC3400 DSP Core Subsystem Block Diagram 3
MSC8144 FC-PBGA Package, Top View . . . . . . . . . . . . 4
MSC8144 FC-PBGA Package, Bottom View . . . . . . . . . 5
SerDes Reference Clocks Input Stage . . . . . . . . . . . . . 31
Start-Up Sequence with V DD Raised Before V DDIO with
Figure 34.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 35.SPI AC Timing in Slave Mode (External Clock). . . . . . .
Figure 36.SPI AC Timing in Master Mode (Internal Clock) . . . . . .
Figure 37.Asynchronous Signal Timing . . . . . . . . . . . . . . . . . . . . .
Figure 38.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 39.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . .
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CLKIN Started with V DDIO . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 7. Timing for a Reset Configuration Write . . . . . . . . . . . . . 38
Figure 8. Timing for t DDKHMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 9. DDR SDRAM Output Timing. . . . . . . . . . . . . . . . . . . . . 41
Figure 10.DDR AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 40.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . .
Figure 41.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 42.V DDM3 , V DDM3IO and V 25M3 Power-on Sequence . . . . .
Figure 44.MSC8144 Mechanical Information, 783-ball FC-PBGA
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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77
Figure 11.Differential V PP of Transmitter or Receiver . . . . . . . . . . 42
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
2
Freescale Semiconductor
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