- 您现在的位置：买卖IC网 > Datasheet目录344 > MSC8144ADS (Freescale Semiconductor)ADS FOR MSC8144 DEVICE Datasheet资料下载
参数资料
| 型号： | MSC8144ADS |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 49/80页 |
| 文件大小： | 0K |
| 描述： | ADS FOR MSC8144 DEVICE |
| 标准包装： | 1 |
| 类型： | DSP |
| 适用于相关产品： | MSC8144 |
| 所含物品： | AMC 卡、电源、缆线、USB TAP、硬件和说明文档 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页当前第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页
Electrical Characteristics
2.6.5.6
Receiver Eye Diagrams
For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the corresponding bit error rate
specification ( Table 32 , Table 33 , and Table 34 ) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter)
falls entirely within the unshaded portion of the receiver input compliance mask shown in Figure 14 with the parameters
specified in Table 35 . The eye pattern of the receiver test signal is measured at the input pins of the receiving device with the
device replaced with a 100 Ω ± 5% differential resistive load.
V DIFF max
V DIFF min
0
–V DIFF min
–V DIFF max
0
A
B
1–B
1–A
1
Time (UI)
Figure 14. Receiver Input Compliance Mask
Table 35. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter
1.25 GBaud
2.5 GBaud
3.125 GBaud
Receiver Type
V DIFF min (mV)
100
100
100
V DIFF max (mV)
800
800
800
A (UI)
0.275
0.275
0.275
B (UI)
0.400
0.400
0.400
2.6.5.7
Measurement and Test Requirements
Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause 47 of IEEE Std.
802.3ae-2002?, the measurement and test requirements defined here are similarly guided by Clause 47. In addition, the CJPAT
test pattern defined in Annex 48A of IEEE Std. 802.3ae-2002 is specified as the test pattern for use in eye pattern and jitter
measurements. Annex 48B of IEEE Std. 802.3ae-2002 is recommended as a reference for additional information on jitter test
methods.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
49
相关PDF资料 |
PDF描述 |
|---|---|
| MSC8156EVM | EVAL MODULE FOR MSC8156 LC |
| MSL1060AW | IC LED DRIVER 6 STRING |
| MSL1061AV | IC LED DRIVER 6 STRING |
| MSL2041GU | IC LED DRIVER 4 STRING |
| MSL2100BR | IC LED DRIVER 8 STRING |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MSC8144AMC-SA | 制造商:Freescale Semiconductor 功能描述:BOARD AMC SGL WIDTH MSC8144 DSP |
| MSC8144E | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Quad Core Digital Signal Processor |
| MSC8144EC | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Quad Core Digital Signal Processor |
| MSC8144ESVT1000B | 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA BOX - Trays 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA |
| MSC8144ESVT800A | 制造商:Freescale Semiconductor 功能描述:DSP 32BIT 800MHZ 800MIPS 783FCBGA - Trays |
发布紧急采购，3分钟左右您将得到回复。