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| 型号： | MSC8144ADS |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 78/80页 |
| 文件大小： | 0K |
| 描述： | ADS FOR MSC8144 DEVICE |
| 标准包装： | 1 |
| 类型： | DSP |
| 适用于相关产品： | MSC8144 |
| 所含物品： | AMC 卡、电源、缆线、USB TAP、硬件和说明文档 |
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Revision History
7
Revision History
Table 66 provides a revision history for this data sheet.
Table 66. Document Revision History
Rev.
0
Date
Feb. 2007
? Initial public release.
Description
1
2
Apr. 2007
June 2007
?
?
?
?
?
?
?
?
?
?
?
?
Adds new I/O multiplexing mode 7 that supports POS functionality.
Updates reference voltage supply for pins G5, H7, and H8 in Table 1 .
Updates start-up timing recommendations with regard to TRST and M3_RESET in Section 2.7.1.
Adds input clock duty cycles in Table 20 .
Updates PCI AC timings in Table 41 .
Removes UTOPIA internal clock specifications in Table 52 .
Updates JTAG timings in Table 56 .
Clarifies connectivity guidelines for Ethernet pins in Section 3.3.4.
Miscellaneous pin connectivity guidelines were updated in Table 71 .
Updates name of core subsystem reference manual.
Corrected AA4 definition in Table 1 . Changed TDM5TD3 to correct name TDM5TDAT.
Removed Figure 35 because the device does not support UTOPIA using an internal clock. Renumbered
subsequent figures.
? Removed Section 3.5 Thermal Considerations . To be replaced with an application note.
78
3
4
5
6
Sep 2007
Sep 2007
Oct 2007
Oct 2007
? Updated M3 voltage range in Table 3 .
? Changed note in Table 7 for PLL power supplies.
? DDR voltage designator changed from V DD to V DDDDR in Table 8 , Table 10 , Section 2.7.4.1 , Section 2.7.4.2 ,
and Figure 11 . Changed range on I OZ in Table 8 and Table 10 .
? Deleted text before Table 13 and added note 2 to input pin capacitance.
? Deleted text before Table 14 , added a 1 to the note, and added note 1 to input pin capacitance.
? Deleted Section 2.6.5 on page 32 and renumbered subsequent subsections.
? Deleted text before new Section 2.6.5.1 .
? Added a 1 to the note in Table 15 and added note 1 to input pin capacitance.
? Deleted ac voltage rows from Table 16 . Added note 1 to input pin capacitance.
? Changed output high and low voltage levels in Table 17 and Table 18 .
? Deleted text before Table 19 .
? Added clock skew ranges in percent in Table 21 .
? Changed V REF to MV REF in Table 26.
? Changed V DD to V DDIO in Table 41 Updated note 2.
? Added note 4 to Table 42 . Changed t TDMSHOX value.
? Changed V DD to V DDGE in Figure 27 and Figure 30 .
? Changed the value of the data to clock out skew in Table 51 .
? Changed EE pin timing in Table 55 .
? Changed the head for the JTAG timing section, now Section 2.7.15 .
? Updated JTAG timing for TCK cycle time, TCK high phase, and boundary scan input data hold time in Table 56 .
? Added new Section 3.3 with guidelines for board layout for clock and timing signals. Renumbered subsequent
sections.
? Changed leakage current values in Table 13 , Table 14 , Table 11 , Table 16 , Table 17 , Table 18 , and Table 19
from –10 and 10 μ a to –30 and 30 μ a.
? Change the minimum value of t MDDVKH in Table 45 from 5 ns to 7 ns.
? Updated note 1 in Table 45 .
? Corrected column numbering in Figure 3 and Figure 4 .
? Updated SPI signal names in Table 1 .
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
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