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| 型号： | MSC8144ADS |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 47/80页 |
| 文件大小： | 0K |
| 描述： | ADS FOR MSC8144 DEVICE |
| 标准包装： | 1 |
| 类型： | DSP |
| 适用于相关产品： | MSC8144 |
| 所含物品： | AMC 卡、电源、缆线、USB TAP、硬件和说明文档 |
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Electrical Characteristics
2.6.5.5
Receiver Specifications
LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section. Receiver input impedance
shall result in a differential return loss better that 10 dB and a common mode return loss better than 6 dB from 100 MHz to 0.8
× baud frequency. This includes contributions from internal circuitry, the package, and any external components related to the
receiver. AC coupling components are included in this requirement. The reference impedance for return loss measurements is
100 Ω resistive for differential return loss and 25 Ω resistive for common mode.
Table 32. Receiver AC Timing Specifications—1.25 GBaud
Range
Characteristic
Symbol
Min
Max
Unit
Notes
Differential Input Voltage
Deterministic Jitter Tolerance
Combined Deterministic and Random
V IN
J D
J DR
200
0.37
0.55
1600
mV PP
UI PP
UI PP
Measured at receiver
Measured at receiver
Measured at receiver
Jitter Tolerance
Total Jitter Tolerance
J T
0.65
UI PP
Measured at receiver. Total jitter is composed of
three components, deterministic jitter, random jitter
and single frequency sinusoidal jitter. The sinusoidal
jitter may have any amplitude and frequency in the
unshaded region of Figure 13 . The sinusoidal jitter
component is included to ensure margin for low
frequency jitter, wander, noise, crosstalk and other
variable system effects.
Multiple Input Skew
S MI
24
ns
Skew at the receiver input between lanes of a
multilane link
Bit Error Rate
BER
10 –12
Unit Interval
UI
800
800
ps
± 100 ppm
Table 33. Receiver AC Timing Specifications—2.5 GBaud
Range
Characteristic
Symbol
Min
Max
Unit
Notes
Differential Input Voltage
Deterministic Jitter Tolerance
Combined Deterministic and Random
V IN
J D
J DR
200
0.37
0.55
1600
mV PP
UI PP
UI PP
Measured at receiver
Measured at receiver
Measured at receiver
Jitter Tolerance
Total Jitter Tolerance
J T
0.65
UI PP
Measured at receiver. Total jitter is composed of
three components, deterministic jitter, random jitter
and single frequency sinusoidal jitter. The sinusoidal
jitter may have any amplitude and frequency in the
unshaded region of Figure 13 . The sinusoidal jitter
component is included to ensure margin for low
frequency jitter, wander, noise, crosstalk and other
variable system effects.
Multiple Input Skew
S MI
24
ns
Skew at the receiver input between lanes of a
multilane link
Bit Error Rate
BER
10 –12
Unit Interval
UI
400
400
ps
± 100 ppm
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
47
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