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| 型号： | NAND512W3A2SN6E |
| 元件分类： | PROM |
| 英文描述： | 64M X 8 FLASH 3V PROM, PDSO48 |
| 封装： | 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48 |
| 文件页数： | 17/51页 |
| 文件大小： | 1009K |
| 代理商： | NAND512W3A2SN6E |
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Device operations
Numonyx SLC SP 70 nm
210403 - Rev 3
6.4
Copy back program
The copy back program operation is used to copy the data stored in one page and
reprogram it in another page.
The copy back program operation does not require external memory and so the operation is
faster and more efficient because the reading and loading cycles are not required. The
operation is particularly useful when a portion of a block is updated and the rest of the block
needs to be copied to the newly assigned block.
If the copy back program operation fails an error is signalled in the status register. However
as the standard external ECC cannot be used with the copy back operation bit error due to
charge loss cannot be detected. For this reason it is recommended to limit the number of
copy back operations on the same data and or to improve the performance of the ECC.
The copy back program operation requires two steps:
1.
The source page must be read using the Read A command (one bus write cycle to
setup the command and then 4 bus write cycles to input the source page address).
This operation copies all 264 Words/ 528 Bytes from the page into the page buffer
2.
When the device returns to the ready state (Ready/Busy High), the second bus write
cycle of the command is given with the 4 bus cycles to input the target page address.
Refer to Table 11 for the addresses that must be the same for the source and target
pages
3.
The Program Confirm command (code 10h) is no more necessary on 512 Mbit, 70 nm
devices. It is optional and has been maintained for backward compatibility.
After a copy back program operation, a partial-page program is not allowed in the target
page until the block has been erased.
See Figure 13 for an example of the copy back operation.
Figure 13.
Copy back operation
1.
The Program Confirm command (code 10h) is no more necessary on 512 Mbit, 70 nm devices. It is optional and has been
maintained for backward compatibility.
Table 11.
Copy back program addresses
Density
Same address for source and target pages
512 Mbit
A25
I/O
RB
Source
Address Inputs
SR0
ai13187
8Ah
70h
00h
Copy Back
Code
Read
Code
Read Status Register
Target
Address Inputs
tBLBH1
(Read Busy time)
10h(1)
Busy
tBLBH2
(Program Busy time)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NAND512W3A2SN6F | 制造商:Micron Technology Inc 功能描述:512MB NAND FLASH 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel |
| NAND512W3A2SZA6E | 制造商:Micron Technology Inc 功能描述:SLC NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 63-Pin VFBGA Tray 制造商:Micron Technology Inc 功能描述:NAND - Trays 制造商:Micron Technology Inc 功能描述:MICNAND512W3A2SZA6E 512MB NAND FLASH 制造商:Micron Technology 功能描述:SLC NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 63-Pin VFBGA Tray |
| NAND512W3A2SZA6F | 制造商:Micron Technology Inc 功能描述:SLC NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 63-Pin VFBGA T/R 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel 制造商:Micron Technology 功能描述:SLC NAND Flash Parallel 3V/3.3V 512Mbit 64M x 8bit 12us 63-Pin VFBGA T/R |
| NAND512W4A0AN6E | 功能描述:闪存 NAND & S.MEDIA FLASH RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| NAND512W4A0AZA6E | 制造商:Micron Technology Inc 功能描述:FLASH PARALLEL 3V/3.3V 512MBIT 32MX16 12US 63VFBGA - Trays |
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