参数资料
型号: NAND512W3A2SN6E
元件分类: PROM
英文描述: 64M X 8 FLASH 3V PROM, PDSO48
封装: 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件页数: 24/51页
文件大小: 1009K
代理商: NAND512W3A2SN6E
Software algorithms
Numonyx SLC SP 70 nm
210403 - Rev 3
7.3
Garbage collection
When a data page needs to be modified, it is faster to write to the first available page, and
the previous page is marked as invalid. After several updates it is necessary to remove
invalid pages to free some memory space.
To free this memory space and allow further program operations it is recommended to
implement a garbage collection algorithm. In a garbage collection software the valid pages
are copied into a free area and the block containing the invalid pages is erased (see
Figure 16.
Garbage collection
7.4
Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a wear-leveling algorithm
to monitor and spread the number of write cycles per block.
In memories that do not use a wear-leveling algorithm not all blocks get used at the same
rate.
The wear-leveling algorithm ensures that equal use is made of all the available write cycles
for each block. There are two wear-leveling levels:
l
First level wear-leveling, new data is programmed to the free blocks that have had the
fewest write cycles
l
Second level wear-leveling, long-lived data is copied to another block so that the
original block can be used for more frequently-changed data.
The second level wear-leveling is triggered when the difference between the maximum and
the minimum number of write cycles per block reaches a specific threshold.
7.5
Error correction code
Users must implement an error correction code (ECC) to identify and correct errors in the
data stored in the NAND Flash memories.
The ECC implemented must be able to correct 1 bit every 512 Bytes. Sensible data stored
in the spare area must be covered by ECC as well.
Valid
page
Invalid
page
Free
page
(erased)
Old area
AI07599B
New area (after GC)
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参数描述
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