88
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
TimingCharacteristics(continued)
Table53.SecondaryCLK(SCLK)Setup/HoldTimewithouton-chipPLLs(Pin-to-Pin)
OR4Exxx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C
< TJ
< +85 °C.
Notes:
1. Thepin-to-pintimingparametersinthistablewillmatchORCAFoundryiftheclockdelaymultiplierinthesetuppreferenceissetto0.95for
setuptimeand1.05forholdtime.
2. Timingiswithouttheuseofthephase-lockedloops(PLLs)orPIOinputFFcyclestealingdelays(whichcanprovidereductionsinsetuptime
attheexpenseofholdtime).
3. Thissetup/holdtimeisforafullyroutedclocktreethatusesthesecondaryclocknetwork.ItincludesboththeLVTTL(3.3V)inputclockbuffer
delay,theclockroutingtothePIOCLKinput,thesetup/holdtimeofthePIOFF(withthedatainputdelaydisabled)andthe
LVTTL(3.3V)inputdatabuffertoPIOFFdelay.AnSCLKinputclockcanbeatanyinputpin.
4. FortimingimprovementsusingotherI/Obuffertypesfortheinputclockbufferorinputdatabuffer,see
Table45.5. TheORT8850HFPSChasslightlyreducedperformancefromthevaluesinthistable.ORCAFoundrywillreporttheactualdelayvaluesfor
alldevices,includingtheORT8850Hinthisarrangement.
5-4847(F).b
Figure50.InputtoSecondaryCLKSetup/HoldTime
Description
Device
Speed
Unit
-1
-2
-3
Min
Max
Min
Max
Min
Max
InputtoSCLKSetupTime(Inputwithin6
PICsofSCLKinput),FastCaptureEnabled
All
5.95
—
5.54
—
5.06
—
ns
InputtoSCLKSetupTime(Inputwithin6
PICsofSCLKinput),NoInputDataDelay
All
0.00
—
0.00
—
0.00
—
ns
ReducedSetupTimepereachextra6PICs
perclockroutedirection.
All
0.36
—
0.38
—
0.34
—
ns
InputtoSCLKHoldTime(Inputwithin6
PICsofSCLKinput),FastCaptureEnabled
All
0.00
—
0.00
—
0.00
—
ns
InputtoSCLKHoldTime(Inputwithin6
PICsofSCLKinput),NoInputDataDelay
All
3.07
—
3.04
—
2.74
—
ns
AdditionalHoldTimepereachextra6PICs
perclockroutedirection.
All
0.36
—
0.38
—
0.34
—
ns
InputDelayAdjustmentsfromPIOCycle
Stealing(typicallyusedtoreducesetuptime
bytheminvalueshown):
OneDelayCell
TwoDelayCells
ThreeDelayCells
ICYCDEL1
ICYCDEL2
ICYCDEL3
—
0.89
1.64
2.43
—
0.70
1.29
1.98
—
0.64
1.18
1.80
ns
Q
D
SCLK
INPUT
PIOFF