44
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Special Function Blocks (continued)
5-5768(F).b
Figure 27. ORCA Series Boundary-Scan Circuitry Functional Diagram
TAP
CONTROLLER
TMS
TCK
BOUNDARY-SCAN REGISTER
ISC READ/WRITE REGISTERS
BYPASS AND ISC_DEFAULT REGISTER
DATA
MUX
INSTRUCTION DECODER
INSTRUCTION REGISTER
M
U
X
RESET
CLOCK IR
SHIFT-IR
UPDATE-IR
PUR
TDO
SELECT
ENABLE
RESET
CLOCK DR
SHIFT-DR
UPDATE-DR
TDI
DATA REGISTERS
PSR1,PSR2,PSR3 REGISTERS (PLCs)
CONFIGURATION REGISTER
(RAM_R, RAM_W)
PRGM
I/O BUFFERS
VDD
IDCODE/USER CODE REGISTER
ORCA Series TAP Controller (TAPC)
The ORCA Series TAP controller (TAPC) is a 1149
compatible test access port controller. The 16 JTAG
state assignments from the IEEE 1149 specication
are used. The TAPC is controlled by TCK and TMS. The
TAPC states are used for loading the IR to allow three
basic functions in testing: providing test stimuli
(Update-DR), test execution (Run-Test/Idle), and
obtaining test responses (Capture-DR). The TAPC
allows the test host to shift in and out both instructions
and test data/results. The inputs and outputs of the
TAPC are provided in the table below. The outputs are
primarily the control signals to the instruction register
and the data register.
Table 20. TAP Controller Input/Outputs
Symbol
I/O
Function
TMS
I
TestModeSelect
TCK
I
TestClock
PUR
I
PowerupReset
PRGM
I
BSCANReset
TRESET
O TestLogicReset
Select
O SelectIR(High);Select-DR(Low)
Enable
O TestDataOutEnable
Capture-DR
O Capture/ParallelLoad-DR
Capture-IR
O Capture/ParallelLoad-IR
Shift-DR
O ShiftDataRegister
Shift-IR
O ShiftInstructionRegister
Update-DR
O Update/ParallelLoad-DR
Update-IR
O Update/ParallelLoad-IR