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Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Embedded Block RAM (EBR) (continued)
Table 8. RAM Signals
Port Signals
I/O
Function
PORT 0
AR0[#:0]
I
Address to be read (variable width depending on RAM size).
AW0[#:0]
I
Address to be written (variable width depending on RAM size).
BW0<1:0>
I
Byte-write enable.
Byte = 8-bits + parity bit.
<1> = bits[17, 15:9] <0> = bits[16, 7:0]
CKR0
I
Positive-edge asynchronous read clock.
CKW0
I
Positive-edge synchronous write clock.
CSR0
I
Enables read to output. Active high.
CSW0
I
Enables write to output. Active high.
D [#:0]
I
Input data to be written to RAM (variable width depending on RAM size).
Q [#:0]
O
Output data of memory contents at referenced address (variable width depending on
RAM size).
PORT 1
AR1[#:0]
I
Address to be read (variable width depending on RAM size).
AW1[#:0]
I
Address to be written (variable width depending on RAM size).
BW1<1:0>
I
Byte-write enable.
Byte = 8-bits + parity bit.
<1> = bits[17, 15:9] <0> = bits[16, 7:0]
CKR1
I
Positive-edge asynchronous read clock.
CKW1
I
Positive-edge synchronous write clock.
CSR1
I
Enables read to output. Active high.
CSW1
I
Enables write to output. Active high.
D [#:0]
I
Input data to be written to RAM (variable width depending on RAM size).
Q [#:0]
O
Output data of memory contents at referenced address (variable width depending on
RAM size).
Control
BUSY
O
PORT1 writing. Active high.
RESET
I
Data output registers cleared. Memory contents unaffected. Active-low.