92
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
TimingCharacteristics(continued)
ConfigurationTiming
Table57.GeneralConfigurationModeTimingCharacteristics
OR4Exxx industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C
< TJ
< +125 °C;CL = 30 pF.
* Not applicable to asynchronous peripheral mode.
Values are shown for the MPI in 32-bit mode with daisy-chaining through the DOUT pin disabled.
Parameter
Symbol
Min
Max
Unit
All Conguration Modes
M[3:0] Setup Time to INIT High
TSMODE
0.00
—
ns
M[3:0] Hold Time from INIT High
THMODE
600.00
—
ns
RESET Pulse Width Low to Start Reconguration
TRW
50.00
—
ns
PRGM Pulse Width Low to Start Reconguration
TPGW
50.00
—
ns
Master and Asynchronous Peripheral Modes
Power-on Reset Delay
CCLK Period (M3 = 0)
(M3 = 1)
Conguration Latency (autoincrement mode, no EBR initialization):
OR4E02
(M3 = 0)
(M3 = 1)
OR4E04
(M3 = 0)
(M3 = 1)
OR4E06
(M3 = 0)
(M3 = 1)
TPO
TCCLK
TCL
15.70
60.00
480.00
69.7
557.6
187.7
1,501.5
284.2
2,273.9
52.40
200.00
1,600.00
232.3
1,858.6
625.6
5,004.9
947.5
7,579.7
ms
ns
ms
Microprocessor (MPI) Mode
Power-on Reset Delay
MPI Clock Period
Conguration Latency (autoincrement mode, no EBR initialization):
OR4E02
OR4E04
OR4E06
TPO
TCL
15.70
15.00
290,412
782,018
1,184,322
52.40
—
ms
MPI clk cycles
Partial Reconguration (per data frame):
OR4E02
OR4E04
OR4E06
TPR
225
321
385
—
MPI clk cycles
Slave Serial Mode
Power-on Reset Delay
CCLK Period
Conguration Latency (autoincrement mode, no EBR initialization):
OR4E02
OR4E04
OR4E06
TPO
TCCLK
TCL
3.90
10.00
11.6
31.3
47.4
13.10
—
ms
ns
ms
Partial Reconguration (per data frame):
OR4E02
OR4E04
OR4E06
TPR
9.0
12.8
15.4
—
s