参数资料
型号: PIC18F45J50-I/ML
厂商: Microchip Technology
文件页数: 36/164页
文件大小: 0K
描述: IC PIC MCU FLASH 32K 2V 44-QFN
产品培训模块: XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
标准包装: 45
系列: PIC® XLP™ 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 48MHz
连通性: I²C,SPI,UART/USART,USB
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 34
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
RAM 容量: 3.8K x 8
电压 - 电源 (Vcc/Vdd): 2.15 V ~ 3.6 V
数据转换器: A/D 13x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-VQFN 裸露焊盘
包装: 管件
产品目录页面: 657 (CN2011-ZH PDF)
配用: AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
PIC18F46J50 FAMILY
DS39931D-page 130
2011 Microchip Technology Inc.
9.6
INTx Pin Interrupts
External interrupts on the INT0, INT1, INT2 and INT3
pins are edge-triggered. If the corresponding INTEDGx
bit in the INTCON2 register is set (= 1), the interrupt is
triggered by a rising edge; if the bit is clear, the trigger
is on the falling edge. When a valid edge appears on
the INTx pin, the corresponding flag bit and INTxIF are
set. This interrupt can be disabled by clearing the
corresponding enable bit, INTxIE. Flag bit, INTxIF,
must be cleared in software in the Interrupt Service
Routine before re-enabling the interrupt.
All external interrupts (INT0, INT1, INT2 and INT3) can
wake-up the processor from Sleep and Idle modes if
bit, INTxIE, was set prior to going into the
power-managed modes. After waking from Sleep or
Idle mode, the processor will branch to the interrupt
vector if the GIEH (and GIEL if configured for low prior-
ity) bit(s) are set. Deep Sleep mode can wake-up from
INT0, but the processor will start execution from the
Power-on Reset vector rather than branch to the
interrupt vector.
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the Interrupt Priority bits,
INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and
INT3IP (INTCON2<1>). There is no priority bit
associated with INT0; it is always a high-priority
interrupt source.
9.7
TMR0 Interrupt
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh
00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L
register pair (FFFFh
0000h) will set TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit, TMR0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP (INTCON2<2>). See
for further details on
the Timer0 module.
9.8
PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
9.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack. If a fast
return from interrupt is not used (see Section 6.3
), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 9-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 9-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
W_TEMP
; W_TEMP is in access bank
MOVFF
STATUS, STATUS_TEMP
; STATUS_TEMP located anywhere
MOVFF
BSR, BSR_TEMP
; BSR_TEMP located anywhere
;
; USER ISR CODE
;
MOVFF
BSR_TEMP, BSR
; Restore BSR
MOVF
W_TEMP, W
; Restore WREG
MOVFF
STATUS_TEMP, STATUS
; Restore STATUS
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