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PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
120
2. Read the XPLS CODE Indirect Data register (register 02FH, 06FH, 0AFH,
0EFH). This returns the code contents of the desired code register.
12.2 Using the Digital Jitter Attenuator
The key to using DJAT lies in selecting the appropriate divisors for the phase
comparison between the selected reference clock and the generated "jitter-free"
clock.
Default Application
Upon reset, the QDSX default condition provides jitter attenuation with the "jitter-
free" clock referenced to the transmit clock TCLKI[X]. The DJAT SYNC bit is also
logic 1 by default. DJAT is configured to divide its input clock rate, TCLKI[X], and
its output "jitter-free" clock rate, both by 48, which is the maximum length of the
FIFO. These divided down clock rates are then used by the phase comparator to
update the DJAT DPLL. The phase delay between TCLKI[X] and the "jitter-free"
clock is synchronized to the physical data delay through the FIFO. For example, if
the phase delay between TCLKI[X] and the "jitter-free" clock is 12 UI (unit
intervals), the FIFO will be forced to lag its output data 12 bits from its input data.
The default mode works well with TCLKI[X] at 1.544MHz for T1 operation format
or at 2.048MHz for E1 operation format.
Data Burst Application
In applications where TCLKI[X] works at a higher than nominal instantaneous
rate (but with gapping to provide the same nominal rate over time), a few factors
must be considered to adequately filter the resultant "jitter-free" clock into a
smooth 1.544MHz or 2.048MHz clock. The magnitude of the phase shifts in the
incoming bursty data are too large to be properly attenuated by the PLL alone.
However, the magnitudes, and the frequency components of these phase shifts
are known, and are most often multiples of 8 kHz.
In this situation, the input clock to DJAT is a gapped bursty clock. The phase
shifts of the input clock with respect to the generated "jitter-free" clock in this
case are large, but when viewed over a longer period, such as a frame, there is
little net phase shift. Therefore, by choosing the divisors appropriately, the large
phase shifts can be filtered out, leaving a stable reference for the DPLL to lock
onto. In this application, the N1 and N2 divisors should be changed to C0H (i.e.
divisors of 193 for T1 applications) or FFH (i.e. divisors of 256 for E1