参数资料
型号: PM4314
厂商: PMC-SIERRA INC
元件分类: 数字传输电路
英文描述: QUAD T1/E1 LINE INTERFACE DEVICE
中文描述: DATACOM, PCM TRANSCEIVER, PQFP128
封装: 14 X 20 MM, PLASTIC, QFP-128
文件页数: 35/170页
文件大小: 823K
代理商: PM4314
PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
23
Pin Name
Type
Pin
No.
Function
CLKO8X/
Output
86
8X Clock Output (CLKO8X).
This output is the internal 8X high-speed clock
derived from the digital jitter attenuator, or
derived by dividing down the 24X XCLK input. It
is used as the reference clock to generate the
transmit analog pulse template. The CLKO8X
signal is generated from Quadrant 1.
1X Clock Output (CLKO1X).
When an 8X clock is provided on XCLK, this is
the internal 8X clock divided by 8. This output
can be used to synchronously clock in data on
TDP[4:1]/TDD[4:1] and TDN[4:1] by connecting it
to TCLKI[4:1].
CLKO1X
Output
DCR
Input
37
Disable Clock Recovery Input (DCR). When set
high, the DCR input will disable clock recovery in
the QDSX and enable the SDP[4:1] and SDN[4:1]
sliced line pulse outputs. This input is logically
"ORed" with the DCR register bits.
TDUAL
Input
66
Transmit Dual-Rail Input Select (TDUAL). This
input selects whether the QDSX expects single-
rail or dual-rail input transmit data. The TDUAL
input is logically "ORed" with the TDUAL register
bits. When TDUAL is set high, the TDP[4:1] and
TDN[4:1] inputs are enabled. When both the
TDUAL input pin and register bits are set low,
then the TDD[4:1] inputs are enabled and the
TDN[4:1] inputs are ignored.
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