参数资料
型号: PM4314
厂商: PMC-SIERRA INC
元件分类: 数字传输电路
英文描述: QUAD T1/E1 LINE INTERFACE DEVICE
中文描述: DATACOM, PCM TRANSCEIVER, PQFP128
封装: 14 X 20 MM, PLASTIC, QFP-128
文件页数: 34/170页
文件大小: 823K
代理商: PM4314
PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
22
Pin Name
Type
Pin
No.
Function
RLCV[4]
RLCV[3]
RLCV[2]
RLCV[1]
Output
88
91
96
99
Receive Line Code Violation Indication
(RLCV[4:1]). When configured for unipolar
outputs, the RLCV[4:1] NRZ outputs pulse
whenever a line code violation or excess zeroes
condition is detected. RDP[4:1] outputs can be
updated on either the falling or rising RCLKO[4:1]
edge.
Receive Digital Positive Pulse (RDN[4:1]). When
configured for bipolar outputs, the RDN[4:1] NRZ
outputs contain sampled bipolar negative pulses.
RDN[4:1] outputs can be updated on either the
falling or rising RCLKO[4:1] edge.
RDN[4]
RDN[3]
RDN[2]
RDN[1]
SDN[4]
SDN[3]
SDN[2]
SDN[1]
Output
Output
Sliced Negative Line Pulse (SDN[4:1]). A positive
pulse on the SDN[4:1] outputs corresponds to the
sampled negative pulse excursion on the
RXTIP[4:1] input.
RCLKO[4]
RCLKO[3]
RCLKO[2]
RCLKO[1]
Output
87
90
95
98
Recovered Clock Output (RCLKO[4:1]).
RCLKO[4:1] is the clock recovered from the
RXTIP[4:1] and RXRING[4:1] input signals.
RCLKO[4:1] are 2mA output pads. Care must be
taken in board layouts to guarantee the integrity
of the clock signals.
XCLK/
Input
79
Crystal Clock Input (XCLK). This signal supplies
the timing reference for the high-speed clocks
required by many portions of the QDSX. When
jitter attenuation is required, XCLK is nominally a
24X clock (37.056 MHz for T1, 49.152 MHz for
E1). When jitter attenuation is not required,
XCLK can be driven by an 8X clock (12.352 MHz
for T1, 16.384 MHz for E1).
Vector Clock (VCLK). The VCLK signal is used
during QDSX production test to verify internal
functionality.
VCLK
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