参数资料
型号: PM4314
厂商: PMC-SIERRA INC
元件分类: 数字传输电路
英文描述: QUAD T1/E1 LINE INTERFACE DEVICE
中文描述: DATACOM, PCM TRANSCEIVER, PQFP128
封装: 14 X 20 MM, PLASTIC, QFP-128
文件页数: 73/170页
文件大小: 823K
代理商: PM4314
PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
61
IBCDTX:
The IBCDTX bit determines whether the IBCD block is placed on the transmit
or receive data paths. When IBCDTX is set to a logic 1, then the IBCD block
is moved to the transmit path and can be used to detect inband loopback
code sequences in the transmit data. When the IBCD block is in the transmit
path, the TDUAL bits (in registers 001H, 041H, 081H, and 0C1H) and the
TDUAL input pin must be set to logic 0 for proper operation. When IBCDTX is
set to a logic 0, then the IBCD block is moved to the receive path will be used
to detect inband loopback code sequences from the analog RXTIP[X] and
RXRING[X] inputs.
XIBCTX:
The XIBCTX bit determines whether the XIBC block is placed on the transmit
or receive data paths. When XIBCTX is set to a logic 1, then the XIBC block
is moved to the transmit path and can be used to insert unframed inband
loopback code sequences into the transmit data. When the TDUAL bit or the
TDUAL pin are logic 1, then the XIBC has no effect if placed the transmit
path. When XIBCTX is set to a logic 0, then the XIBC block is moved to the
receive path and can be used to source an unframed inband loopback code
sequence to the RDD[X] output.
DJATTX:
The DJAT bit determines whether the DJAT block is placed on the transmit or
receive data paths. When DJATTX is set to a logic 1, then the DJAT block is
moved to the transmit path to attenuate jitter in the transmit data stream.
When DJATTX is set to a logic 0, then the DJAT block is moved to the receive
path and will attenuate the jitter on the RDD/RDP[X], RLCV/RDN[X], and
RCLKO[X] outputs. Note that a 24X clock must be input on XCLK for jitter
attenuation to operate (see TOPS Clock Timing Options register 00AH, 04AH,
08AH, and 0CAH and TOPS Master Clock Configuration/Clock activity
monitor register 009H). Whenever the DJAT is not active in the transmit path,
the system 8X clock (presented on CLK08X) must be synchronous to
TCLKI[X], and line loopback cannot be used. Refer to the operations section
for more details on using the QDSX without the DJAT enabled in the transmit
path.
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