PMC-Sierra, Inc.
PM73121AAL1gator II
L
PMC-980620
,VVXH
AAL1 SAR Processor
Data Sheet
35235,(7$5<$1'&21),'(17,$/7230&6,(55$,1&$1')25,76&86720(56,17(51$/86(
Figure 70 shows the timing information for all RAM read cycles.
6.5.2
Microprocessor Timing
Microprocessor accesses are controlled by the AAL1gator II. To properly access the
AAL1gator II and the external memory, the AAL1gator II must be supported with a tristatable
address buffer and a bidirectional tristatable data latch.
6.5.2.1
Microprocessor RAM Write Cycle Timing
Figure 71 on page 107
shows the timing for a microprocessor-initiated write cycle. It shows the
2-cycle write operation occurring immediately after a non-processor read cycle. RAM writing is
not honored if higher priority internal functions request the memory, or the holdoff from a previ-
ous microprocessor transfer has not expired. /PROC_CS and /PROC_WR are double sampled (1
and 2) with the rising edge of SYS_CLK, and at (3) ADDR17 is sampled to distinguish between a
command register write and a RAM write.
Figure 70.
RAM Read Cycle Timing
Symbol
Parameter
Signals
Min
Max
Unit
Toe
RAM output enable delay
MEM_DATA
0
7
ns
Trc
Read cycle
/MEM_CS
Tp-2
ns
Trdacc
Read access time
MEM_DATA, /MEM_CS, /MEM_
ADDR
16 + Tsc
ns
NOTES:
Tsc = (1
÷
Fc) - (1
÷
38.87 MHz). For Fc and Tp values, see
Figure 80 on page 119
.
Test conditions are: /MEM_WE(0) and /MEM_WE(1) at 15 pF; and MEM_DATA, SP_DATA_EN, SP_
DATA_CLK, SP_DATA_DIR, and /MEM_CS at 30 pF; MEM_ADDR and SP_ADDR_EN at 40 pF.
All outputs are measured at 1.5 V, -40 to 85
°
C, 4.75 - 5.25 V.
Trc
Trdacc
Toe
Trdacc
/MEM_CS(o)
/MEM_OE(o)
MEM_ADDR(io)
MEM_DATA(io)
/MEM_WE(o)