PMC-Sierra, Inc.
PM73121AAL1gator II
L
PMC-980620
,VVXH
AAL1 SAR Processor
Data Sheet
35235,(7$5<$1'&21),'(17,$/7230&6,(55$,1&$1')25,76&86720(56,17(51$/86(
NOTE: Taa is dependent on the HOLDOFF signal. If HOLDOFF is not asserted when the
access begins, Taa will be a maximum of seven SYS_CLK periods. If the access
occurs immediately after another access, then Taa will be 23 to 29 SYS_CLK peri-
ods. Refer to section 6.5.3 “Microprocessor Holdoff Timing” for a description of
HOLDOFF activity.
6.5.3
Microprocessor Holdoff Timing
Figure 75 on page 116
shows the microprocessor holdoff timing. After the microprocessor
accesses the AAL1gator II, the holdoff circuit prevents the microprocessor from obtaining
another back-to-back access for 20 SYS_CLK cycles. However, holdoff does not apply while
SW_RESET, in the command register is set. The AAL1gator II holdoff counter is activated after
every processor access that occurs while the device is not in the RESET state. The holdoff counter
counts up to 20 and then freezes at that count. Microprocessor accesses are not honored unless
this count has completed.
Symbol
Parameter
Signals
Min
Max
Unit
Taa
(Refer to
NOTE below)
Acknowledge assertion after /CS
or /RD, whichever comes last
/PROC_ACK
5
29
SYS_CLK
periods
Tasu17
Address setup time
MEM_ADDR
2
ns
Trd
Read operation time
4
4
SYS_CLK
periods
Tq
Clock-to-output delay
SP_DATA_CLK
2
15
ns
Tded
Data enable delay from /MEM_
CS and /MEM_RD
/SP_DATA_EN, /MEM_CS,
/MEM_RD
2
15
ns
Tdsu
Data setup to SP_DATA_CLK
MEM_DATA
15
ns
Tdhld
Data hold from SP_DATA_CLK
MEM_DATA
15
ns
Tcea
/PROC_CS deassertion to
/PROC_ACK deassertion
/PROC_ACK
2
15
ns
Figure 75.
Microprocessor Holdoff Timing
Thoff
/PROC_CS(i)
HOLDOFF(o)