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参数资料
| 型号： | PSD835G2V-A-20J |
| 厂商： | 意法半导体 |
| 英文描述： | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| 中文描述： | 在8片位微控制器可配置存储系统 |
| 文件页数： | 23/110页 |
| 文件大小： | 570K |
| 代理商： | PSD835G2V-A-20J |
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PSD8XX Family
PSD835G2
22
9.1.1.7 Programming Flash Memory
Flash memory must be erased prior to being programmed. The MCU may erase Flash
memory all at once or by-sector. Flash memory sector erases to all logic ones (FF hex),
and its bits are programmed to logic zeros. Although erasing Flash memory occurs on a
sector basis, programming Flash memory occurs on a word basis.
The PSD835G2 main Flash and secondary Flash memories require the MCU to send an
instruction to program a word or perform an erase function (see Table 8).
Once the MCU issues a Flash memory program or erase instruction, it must check for the
status of completion. The embedded algorithms that are invoked inside the PSD835G2
support several means to provide status to the MCU. Status may be checked using any of
three methods: Data Polling, Data Toggle, or the Ready/Busy output pin.
9.1.1.7.1 Data Polling
Polling on DQ7 is a method of checking whether a Program or Erase instruction is in
progress or has completed. Figure 4 shows the Data Polling algorithm.
When the MCU issues a programming instruction, the embedded algorithm within the
PSD835G2 begins. The MCU then reads the location of the word to be programmed in
Flash to check status. Data bit DQ7 of this location becomes the compliment of data
bit 7of the original data word to be programmed. The MCU continues to poll this location,
comparing DQ7 and monitoring the Error bit on DQ5. When the DQ7 matches data bit 7 of
the original data, and the Error bit at DQ5 remains
‘
0
’
, then the embedded algorithm is
complete. If the Error bit at DQ5 is
‘
1
’
, the MCU should test DQ7 again since DQ7 may
have changed simultaneously with DQ5 (see Figure 4).
The Error bit at DQ5 will be set if either an internal timeout occurred while the embedded
algorithm attempted to program the location or if the MCU attempted to program a
‘
1
’
to a
bit that was not erased (not erased is logic
‘
0
’
).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed to compare the word that was written to Flash with
the word that was intended to be written.
When using the Data Polling method after an erase instruction, Figure 4 still applies.
However, DQ7 will be
‘
0
’
until the erase operation is complete. A
‘
1
’
on DQ5 will indicate
a timeout failure of the erase operation, a
‘
0
’
indicates no error. The MCU can read any
location within the sector being erased to get DQ7 and DQ5.
PSDsoft generates ANSI C code functions which implement these Data Polling
algorithms.
The
PSD835G2
Functional
Blocks
(cont.)
相关PDF资料 |
PDF描述 |
|---|---|
| PSD835G2V-A-20JI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G2V-A-20M | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G2V-A-20MI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G2V-A-20U | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G2V-A-20UI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PSD853F2-70J | 功能描述:SPLD - 简单可编程逻辑器件 5.0V 1M 70ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
| PSD853F2-70M | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 70ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD853F2-90J | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD853F2-90JI | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD853F2-90M | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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