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参数资料
型号： PSD835G2V-A-20J
厂商： 意法半导体
英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述： 在8片位微控制器可配置存储系统
文件页数： 44/110页
文件大小： 570K
代理商： PSD835G2V-A-20J
PSD835G2
PSD8XX Family
43
The
PSD835G2
Functional
Blocks
(cont.)
9.3 Microcontroller Bus Interface
The
“
no-glue logic
”
PSD835G2 Microcontroller Bus Interface can be directly connected to
most popular microcontrollers and their control signals. Key 8-bit microcontrollers with their
bus types and control signals are shown in Table 14. The MCU interface type is
specified using the PSDsoft.
9.3.1. PSD835G2 Interface to a Multiplexed Bus
Figure 17 shows an example of a system using a microcontroller with a 8-bit multiplexed
bus and a PSD835G2. The ADIO port on the PSD835G2 is connected directly to the
microcontroller address/data bus. ALE latches the address lines internally. Latched
addresses can be brought out to Port E, F or G. The PSD835G2 drives the ADIO data bus
only when one of its internal resources is accessed and the RD input is active. Should the
system address bus exceed sixteen bits, Ports A, B, C, or F may be used as additional
address inputs.
9.3.2. PSD835G2 Interface to a Non-Multiplexed Bus
Figure 18 shows an example of a system using a microcontroller with a 8-bit
non-multiplexed bus and a PSD835G2. The address bus is connected to the ADIO Port,
and the data bus is connected to Port F. Port F is in tri-state mode when the PSD835G2
is not accessed by the microcontroller. Should the system address bus exceed sixteen
bits, Ports A, B or C may be used for additional address inputs.
Data
Bus
Width
MCU
CNTL0
CNTL1
CNTL2
PC7
*
*
*
*
*
*
*
DBE
*
*
*
*
PD0**
ADIO0
PF3-PF0 PF7-PF4
*
A3-A0
*
*
*
*
*
*
D3-D0
*
*
D3-D0
8031/8051
80C51XA
80C251
80C251
80198
68HC11
68HC05C0
68HC912
Z80
Z8
68330
M37702M2
8
8
8
8
8
8
8
8
8
8
8
8
WR
WR
WR
WR
WR
R/W
WR
R/W
WR
R/W
R/W
R/W
RD
RD
PSEN
RD
RD
E
RD
E
RD
DS
DS
E
PSEN
PSEN
*
PSEN
*
*
*
*
*
*
*
*
ALE
ALE
ALE
ALE
ALE
AS
AS
AS
*
AS
AS
ALE
A0
A4
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
*
*
*
*
*
*
*
*
D7-D4
*
*
D7-D4
Table 14. Microcontrollers and their Control Signals
*
*
Unused CNTL2 pin can be configured as PLD input. Other unused pins (PD3-0, PA3-0) can be
**
configured for other I/O functions.
**
ALE/AS input is optional for microcontrollers with a non-multiplexed bus
相关PDF资料
PDF描述
PSD835G2V-A-20JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2V-A-20M Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2V-A-20MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2V-A-20U Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2V-A-20UI Configurable Memory System on a Chip for 8-Bit Microcontrollers
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