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参数资料
| 型号： | PSD835G2V-A-20J |
| 厂商： | 意法半导体 |
| 英文描述： | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| 中文描述： | 在8片位微控制器可配置存储系统 |
| 文件页数： | 69/110页 |
| 文件大小： | 570K |
| 代理商： | PSD835G2V-A-20J |
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PSD8XX Family
PSD835G2
68
APD
ALE
Enable Bit
0
1
1
1
PD Polarity
X
X
1
0
ALE Level
X
Pulsing
1
0
APD Counter
Not Counting
Not Counting
Counting (Generates PDN after 15 Clocks)
Counting (Generates PDN after 15 Clocks)
Table 28. APD Counter Operation
The
PSD835G2
Functional
Blocks
(cont.)
9.5.2 Other Power Saving Options
The PSD835G2 offers other reduced power saving options that are independent of the
Power Down Mode. Except for the SRAM Standby and CSI input features, they are
enabled by setting bits in the PMMR0 and PMMR2 registers.
9.5.2.1 Zero Power PLD
The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in the PMMR0.
By setting the bit to “1”, the Turbo mode is disabled and the PLDs consume Zero Power
current when the inputs are not switching for an extended time of 70 ns. The propagation
delay time will be increased after the Turbo bit is set to “1” (turned off) when the inputs
change at a composite frequency of less than 15 MHz. When the Turbo bit is set to a “0”
(turned on), the PLDs run at full power and speed. The Turbo bit affects the PLD’s D.C.
power, AC power, and propagation delay. Refer to AC/DC spec for PLD timings.
Note:
Blocking MCU control signals with PMMR2 bits can further reduce PLD AC power
consumption.
9.5.2.2 SRAM Standby Mode (Battery Backup)
The PSD835G2 supports a battery backup operation that retains the contents of the SRAM
in the event of a power loss. The SRAM has a Vstby pin (PE6) that can be connected to
an external battery. When V
CC
becomes lower than Vstby then the PSD will automatically
connect to Vstby as a power source to the SRAM. The SRAM Standby Current (Istby) is
typically 0.5 μA. The SRAM data retention voltage is 2 V minimum. The battery-on
indicator (Vbaton) can be routed to PE7. This signal indicates when the V
CC
has dropped
below the Vstby voltage and that the SRAM is running on battery power.
9.5.2.3 The CSI Input
Pin PD2 of Port D can be configured in PSDsoft as the CSI input. When low, the signal
selects and enables the internal Flash, Boot Block, SRAM, and I/O for read or write
operations involving the PSD835G2. A high on the CSI pin will disable the Flash memory,
Boot Block, and SRAM, and reduce the PSD power consumption. However, the PLD and
I/O pins remain operational when CSI is high.
Note:
there may be a timing penalty when
using the CSI pin depending on the speed grade of the PSD that you are using. See the
timing parameter t
SLQV
in the AC/DC specs.
9.5.2.4 Input Clock
The PSD4000 provides the option to turn off the CLKIN input to the PLD to save AC
power consumption. The CLKIN is an input to the PLD AND array and the Output
Micro
Cells. During Power Down Mode, or, if the CLKIN input is not being used as part of
the PLD logic equation, the clock should be disabled to save AC power. The CLKIN will be
disconnected from the PLD AND array or the Micro
Cells by setting bits 4 or 5 to a “1” in
PMMR0.
9.5.2.5 MCU Control Signals
The PSD835G2 provides the option to turn off the address input (A7-0) and input control
signals (CNTL0-2, ALE, and DBE) to the PLD to save AC power consumption. These
signals are inputs to the PLD AND array. During Power Down Mode, or, if any of them are
not being used as part of the PLD logic equation, these control signals should be disabled
to save AC power. They will be disconnected from the PLD AND array by setting bits 0, 2,
3, 4, 5, and 6 to a “1” in the PMMR2.
相关PDF资料 |
PDF描述 |
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| PSD835G2V-A-20JI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PSD853F2-70J | 功能描述:SPLD - 简单可编程逻辑器件 5.0V 1M 70ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
| PSD853F2-70M | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 70ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD853F2-90J | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD853F2-90JI | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD853F2-90M | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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