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参数资料
| 型号： | PSD835G2V-A-20J |
| 厂商： | 意法半导体 |
| 英文描述： | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| 中文描述： | 在8片位微控制器可配置存储系统 |
| 文件页数： | 57/110页 |
| 文件大小： | 570K |
| 代理商： | PSD835G2V-A-20J |
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PSD8XX Family
PSD835G2
56
The
PSD835G2
Functional
Blocks
(cont.)
MCU
Port E (3:0)
Port E (7:4)
Port F (3:0)
Port F (7:4)
Port G (3:0)
Port G (7:4)
80C51XA
N/A
*
Addr (7:4)
N/A
*
Addr (7:4)
Addr (11:8)
N/A
80C251
(Page Mode)
N/A
N/A
N/A
N/A
Addr (11:8)
Addr (15:12)
All Other
Eight-Bit
Multiplexed
Addr (3:0)
Addr (7:4)
Addr (3:0)
Addr (7:4)
Addr (3:0)
Addr (7:4)
8-Bit
Non-Mux
Bus
N/A
N/A
N/A
N/A
Addr (3:0)
Addr (7:4)
Table 18. I/OPort Latched Address Output Assignments
9.4.2.4 Address In Mode
For microcontrollers that have more than 16 address lines, the higher addresses can be
connected to Ports A, B, C, D or F and are routed as inputs to the PLDs. The address
input can be latched in the Input Micro
Cell by the address strobe (ALE/AS). Any
input that is included in the DPLD equations for the Main Flash, Boot Flash, or SRAM is
considered to be an address input.
9.4.2.5 Data Port Mode
Port F can be used as a data bus port for a microcontroller with a non-multiplexed
address/data bus. The Data Port is connected to the data bus of the microcontroller. The
general I/O functions are disabled in Port F if the ports are configured as Data Port. Data
Port Mode is automatically configured in PSDsoft when a non-multiplexed bus MCU is
selected.
9.4.2.6 Peripheral I/OMode
Peripheral I/O Mode can be used to interface with external 8-bit peripherals. In this mode,
all of Port F serves as a tri-stateable, bi-directional data buffer for the microcontroller.
Peripheral I/O Mode is enabled by setting Bit 7 of the VM Register to a ‘1’. Figure 25
shows how Port A acts as a bi-directional buffer for the microcontroller data bus if
Peripheral I/O Mode is enabled. An equation for PSEL0 and/or PSEL1 must be specified in
PSDsoft. The buffer is tri-stated when PSEL 0 or 1 is not active.
9.4.2.7 JTAG ISP
Port E is JTAG compliant, and can be used for In-System Programming (ISP). You can
multiplex JTAG operations with other functions on Port E because ISP is not performed
during normal system operation. For more information on the JTAG Port, refer to
section 9.6.
9.4.2.3 Address Out Mode
For microcontrollers with a multiplexed address/data bus, Address Out Mode can be used
to drive latched addresses onto the port pins. These port pins can, in turn, drive external
devices. Either the output enable or the corresponding bits of both the Direction Register
and Control Register must be set to a ‘1’ for pins to use Address Out Mode. This must be
done by the MCU at run-time. See Table 18 for the address output pin assignments on
Ports E, F and F for various MCUs.
Note:
Do not drive address lines with Address Out Mode to an external memory device if
it is intended for the MCU to boot from the external device. The MCU must first boot from
PSD memory so the Direction and Control register bits can be set.
相关PDF资料 |
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相关代理商/技术参数 |
参数描述 |
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| PSD853F2-70J | 功能描述:SPLD - 简单可编程逻辑器件 5.0V 1M 70ns RoHS:否 制造商:Texas Instruments 逻辑系列:TICPAL22V10Z 大电池数量:10 最大工作频率:66 MHz 延迟时间:25 ns 工作电源电压:4.75 V to 5.25 V 电源电流:100 uA 最大工作温度:+ 75 C 最小工作温度:0 C 安装风格:Through Hole 封装 / 箱体:DIP-24 |
| PSD853F2-70M | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 70ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD853F2-90J | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD853F2-90JI | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| PSD853F2-90M | 功能描述:CPLD - 复杂可编程逻辑器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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