
R8C/38T-A Group
14. I/O Ports
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 201 of 730
Aug 05, 2011
Table 14.4
I/O Port Pin Assignment Information by Pin Number for 80-Pin Product
Pin No
Standard Assignment
Pin No
Standard Assignment
1
P5_6/CH27
41
P8_3/CHxA1
2
P5_5/TRJIO_0/CH26
42
P8_2/CHxA0
3
P3_2/INT2/TRJIO_0/INT1/CH25
43
P8_1/CH07
4
P3_0/TRJO_0/CH24
44
P8_0/CH06
5
P4_2/VREF
45
P6_7/INT3/TRCIOD_0/CH05
6
MODE
46
P6_6/INT2/TXD2/SDA2/TRCIOC_0/CH04
7
P4_3/XCIN
47
P6_5/INT4/CLK2/CLK_1/TRCIOB_0/CH03
8
P4_4/XCOUT
48
P4_5/INT0/RXD2/SCL2/ADTRG/CH02
9
RESET
49
P1_7/INT1/IVCMP1/CH01
10
P4_7/XOUT
50
P1_6/CLK_0/IVREF1/CH00
11
VSS/AVSS
51
P1_5/RXD_0/TRJIO_0/INT1
12
P4_6/XIN
52
P1_4/TXD_0/TRCCLK_0
13
VCC/AVCC
53
P1_3/KI3/AN11/TRBO_0/TRCIOC_0
14
P5_4/TRCIOD_0
54
P1_2/KI2/AN10/TRCIOB_0
15
P5_3/TRCIOC_0
55
P1_1/KI1/AN9/TRCIOA_0/TRCTRG_0
16
P5_2/TRCIOB_0
56
P1_0/KI0/AN8/TRCIOD_0
17
P5_1/TRCIOA_0/TRCTRG_0
57
P7_7/AN19
18
P5_0/TRCCLK_0
58
P7_6/AN18
19
P3_7/SSO_0/TXD2/SDA2/RXD2/SCL2/SDA_0
59
P7_5/AN17
20
P3_5/SCL_0/SSCK_0/TRCIOD_0/CLK2
60
P7_4/AN16
21
P3_4/TRCIOC_0/SSI_0/RXD2/SCL2/TXD2/SDA2/IVREF3
61
P7_3/AN15
22
P3_3/INT3/TRCCLK_0/SCS_0/CTS2/RTS2/IVCMP3
62
P7_2/AN14
23
P2_7/CH23
63
P7_1/AN13
24
P2_6/CH22
64
P7_0/AN12
25
P2_5/CH21
65
P0_7/AN0/TRCIOC_0
26
P2_4/CH20
66
P0_6/AN1/TRCIOD_0
27
P2_3/CH19
67
P0_5/AN2/TRCIOB_0
28
P2_2/TRCIOD_0/CH18
68
P0_4/AN3/TMRE2O/TRCIOB_0
29
P2_1/TRCIOC_0/CH17
69
P0_3/AN4/CLK_1/TRCIOB_0
30
P2_0/INT1/TRCIOB_0/CH16
70
P0_2/AN5/RXD_1/TRCIOA_0/TRCTRG_0
31
P9_3/CH15
71
P0_1/AN6/TXD_1/TRCIOA_0/TRCTRG_0
32
P9_2/CH14
72
P0_0/AN7/TRCIOA_0/TRCTRG_0
33
P9_1/CH13
73
P6_4/RXD_1/CH35
34
P9_0/CH12
74
P6_3/TXD_1/CH34
35
P3_6/CH11
75
P6_2/CLK_1/CH33
36
P3_1/CH10
76
P6_1/CH32
37
P8_7/CH09
77
P6_0/TMRE2O/CH31
38
P8_6/CH08
78
P9_5/CH30
39
P8_5/CHxC
79
P9_4/CH29
40
P8_4/CHxB
80
P5_7/CH28