
R8C/38T-A Group
17. Timer RC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 302 of 730
Aug 05, 2011
17.3.2
PWM Mode
In PWM mode, when the TRCGRA register is set as the period register and registers TRCGRB, TRCGRC, and
TRCGRD are set as the duty registers, a PWM waveform is output from pins TRCIOB, TRCIOC, and TRCIOD
individually. A PWM waveform with up to three phases can be output. In this mode, the general register
functions as an output compare register. The initial output level of the corresponding pin is set according to the
set values of bits TOA to TOD in the TRCCR1 register and bits POLB to POLD in the TRCCR2 register.
For TRCIOB, TRCIOC, and TRCIOD output, if the initial value until compare match is the same as the set
value for the active polarity at compare match, the compare match output is actually performed, but because the
output value does not change during output it will appear as if the initial value were retained.
The output level is determined by bits POLB to POLD. When the POLB bit is 0 (output level is active low), the
TRCIOB output pin is set to low at compare match B and high at compare match A. When the POLB bit is 1
(output level is active high), the TRCIOB output pin is set to high at compare match B and low at compare
match A.
The setting values of PWM mode take precedence over those of registers TRCIOR0 and TRCIOR1. When the
values set in the period and duty registers are the same, the output value remains unchanged even if a compare
match occurs.
Table 17.11
Initial Output Levels of TRCIOB Pin
TOB Bit in TRCCR1 Register
POLB Bit in TRCCR2 Register
Initial Output Level
0
01
10
1
00
11