
R8C/38T-A Group
11. Interrupts
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 146 of 730
Aug 05, 2011
11.4.5
Interrupt Response Time
interrupt request is generated until the first instruction in the interrupt routine is executed. This time consists of
two periods: the first period ranges from when an interrupt request is generated until the currently executing
instruction is completed ((a) in
Figure 11.4) and the second from when an interrupt request is acknowledged
until the interrupt sequence is executed (20 cycles (b)).
Figure 11.4
Interrupt Response Time
11.4.6
IPL Change when Interrupt Request is Acknowledged
When a maskable interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt
is set in the IPL.
For a software interrupt or special interrupt request, the level listed in
Table 11.8 is set in the IPL.
Table 11.8
IPL Value when Software or Special Interrupt is Acknowledged
Interrupt Source without Interrupt Priority Level
Value Set in IPL
Watchdog timer, oscillation stop detection, voltage monitor 1,
voltage monitor 2, address break
7
Software, address match, single-step
Not changed
(a) The period from when an interrupt request is generated until the currently executing instruction is completed .
The length of this time varies with the instruction being executed . The DIVX instruction requires the longest
time, 30 cycles (no wait states, and the divisor is a register).
(b) 21 cycles for address match and single-step interrupts.
Interrupt request
generated
Interrupt request
acknowledged
Time
(a)
20 cycles (b)
Interrupt response time
Instruction
Interrupt sequence
Instruction in
interrupt routine