
R8C/38T-A Group
9. Clock Generation Circuit
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 86 of 730
Aug 05, 2011
Figure 9.1
Clock Generation Circuit Block Diagram
S Q
R
Charge/
discharge
circuit
Oscillation stop detection
Interrupt generation circuit
S Q
R
FRA00
High-speed
on-chip
oscillator
FRA01 = 1
FRA01 = 0
CM14
1/1
1/2
1/4
1/8
Divider
XIN clock
XOUT
CM02
WAIT instruction
CM10 = 1 (stop mode)
Oscillation Stop Detection Circuit
Pulse generation
circuit for clock edge
detection and
charge/discharge
control
XIN clock
Forcible discharge when OCD0 = 0
Watchdog timer interrupt
OCD1
Oscillation stop detection,
watchdog timer,
voltage monitor 1 interrupt,
voltage monitor 2 interrupt
CM02 to CM06: Bits in CM0 register
CM10, CM13, CM14, CM16, CM17: Bits in CM1 register
CM30: Bit in CM3 register
CM40 to CM42: Bits in CM4 register
OCD0, OCD1: Bits in OCD register
FRA00, FRA01, FRA03: Bits in FRA0 register
FRA20 to FRA22, FRA24, FRA25: Bits in FRA2 register
CSPRO: Bit in CSPR register
FRA20 to FRA22
fOCO (on-chip oscillator clock)
fLOCO
1/32
Voltage monitor 2 interrupt
System clock
Low-speed
on-chip
oscillator
Registers FRA24 and FRA25
Frequency adjustable
Divider
fC1
Power-on reset
circuit
Voltage
detection circuit
Voltage monitor 1 interrupt
Divider
(1/128)
1/8
1/2
CPU clock
f1
f2
f4
f8
f32
fHOCO
fC32
fHOCO-F
fOCO
fOCO128
fLOCO
Peripheral
function clocks
1/2
fC1
fLOCOWDT
Low-speed on-chip oscillator
for watchdog timer
CSPRO
CM30
CM13
CM05
XIN
CM13
CM04
CM03
XCIN
CM04
XCOUT
FRA03 = 1
FRA03 = 0
RESET
Power-on reset
Software reset
Interrupt request
Voltage monitor 0 reset
XCIN clock
fHOCO-F
XIN clock
fLOCO
Selected by
CM40 to CM42
Selected by
CM06, CM16, and CM17
XCIN clock
fC2
Oscillation
stop
detection