
R8C/38T-A Group
19. Serial Interface (UART0)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 377 of 730
Aug 05, 2011
19. Serial Interface (UART0)
The serial interface consists of two channels: UART0_0 and UART0_1.
This chapter describes these channels as UART0 unless there are differences between them.
19.1
Overview
Each UART0 channel is independent and has a dedicated timer for generating a transfer clock. It supports two
modes: Clock synchronous serial I/O mode and clock asynchronous serial I/O (UART) mode.
Table 19.1
UART0 Specifications
Item
Description
Clock
synchronous
serial I/O
mode
Transfer data
format
Transfer data length: 8 bits
Transfer clock
The CKDIR bit in the U0MR register is 0 (internal clock): fi/2 (n + 1)
fi = f1, f8, f32, or fC1
n: Value set in the U0BRG register (00h to FFh)
The CKDIR bit in the U0MR register is 1 (external clock):
fEXT (input from the CLK pin)
Error detection
Overrun error
Clock
asynchronous
serial I/O
mode
Transfer data
format
Character bits (transfer data): 7, 8, or 9 bits selectable
Start bit: 1 bit
Parity bit: Odd, even, or none selectable
Stop bit: 1 or 2 bits selectable
Transfer clock
The CKDIR bit in the U0MR register is 0 (internal clock): fj/16 (n + 1)
fj = f1, f8, f32, or fC1
n: Value set in the U0BRG register (00h to FFh)
The CKDIR bit in the U0MR register is 1 (external clock): fEXT/16 (n + 1)
fEXT (input from the CLK pin)
n: Value set in the U0BRG register (00h to FFh)
Error detection
Overrun error, framing error, parity error, error sum flag
Interrupt sources
Transmit buffer empty or transmission complete interrupt (multiplexed), and
reception complete interrupt