
R8C/38T-A Group
19. Serial Interface (UART0)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 393 of 730
Aug 05, 2011
19.3.2.1
Operation Examples
Figure 19.6
Transmit Timing in Clock Asynchronous Serial I/O Mode
Transfer clock
TE bit in
U0C1 register
TI bit in
U0C1 register
The above diagram applies for the following settings:
STPS bit in U0MR register = 0 (one stop bit)
PRYE bit in U0MR register = 1 (parity enabled)
U0IRS bit in U0C1 register = 1 (transmission completed)
TC = 16 (n + 1)/fj or 16 (n + 1)/fEXT
fj: Frequency of U0BRG count source (f1, f8, f32, or fC1)
fEXT: Frequency of U0BRG count source (external clock)
n: Value set in U0BRG register
TXD
TXEPT bit in
U0C0 register
Stop
bit
Parity
bit
Stopped because TE bit is 0
When transfer data is 8 bits long (parity enabled, one stop bit)
From U0TB register to UART0 transmit register
Start
bit
TC
Transfer clock
TE bit in
U0C1 register
TI bit in
U0C1 register
The above diagram applies for the following settings:
STPS bit in U0MR register = 1 (two stop bits)
PRYE bit in U0MR register = 0 (parity disabled)
U0IRS bit in U0C1 register = 0 (transmit buffer empty)
TXD
TXEPT bit in
U0C0 register
Stop bit
When transfer data is 9 bits long (parity disabled, two stop bits)
Start
bit
From U0TB register to UART0 transmit register
TC = 16 (n + 1)/fj or 16 (n + 1)/fEXT
fj: Frequency of U0BRG count source (f1, f8, f32, or fC1)
fEXT: Frequency of U0BRG count source (external clock)
n: Value set in U0BRG register
TC
1/fj
TC/2 + 1/fj
1/fj
D1 D2 D3 D4 D5
D2 D3 D4 D5 D6
D0
ST
D1
D6 D7
D0
P
ST
SP
D7 P
SP
ST
D1 D2 D3 D4 D5 D6 D7 D8 SP SP
D0
ST
D2 D3 D4 D5 D6
D1
D0
ST
D7 D8 SP SP
D0
ST
Data is set in U0TB register