R8C/38T-A Group
8. Watchdog Timer
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 75 of 730
Aug 05, 2011
8.
Watchdog Timer
The watchdog timer is a function for detecting software malfunctions. Using this function is recommended, since it can
improve system reliability.
8.1
Overview
The watchdog timer has a 14-bit down counter and count source protection mode can be enabled or disabled.
Note:
1. Only write to the WDTR register during the refresh period when the watchdog timer is counting.
Table 8.1
Watchdog Timer Specifications
Item
Count Source Protection Mode Disabled
Count Source Protection Mode Enabled
Count source
CPU clock or low-speed on-chip oscillator
clock for the watchdog timer (1/16)
Low-speed on-chip oscillator clock for the
watchdog timer
Count operation
Decrement
Count start condition
Either of the following can be selected:
The count is automatically started after a reset.
The count is started by writing to the WDTS register.
Count stop conditions
When the count source is the CPU clock
divided by 2, 16, or 128, if the MCU enters
wait mode or stop mode, the count is
stopped.
When the count source is the watchdog
timer low-speed on-chip oscillator clock
divided by 16, even if the MCU enters wait
mode or stop mode, the count is not
stopped.
None
Watchdog timer
initialization conditions
Reset
00h and then FFh are written to the WDTR register during the acceptance period
(1)(when an acceptance period is set.)
Underflow
Operation at underflow Watchdog timer interrupt or watchdog timer
reset
Watchdog timer reset
Selectable functions
Prescaler division ratio
Selected by bits WDTC6 and WDTC7 in the WDTC register.
Count source protection mode
- Whether count source protection mode is enabled or disabled after a reset can be
selected by the CSPROINI bit in the OFS register (flash memory).
- If count source protection mode is disabled, whether count source protection mode is
enabled or disabled is selected by the CSPRO bit in the CSPR register (program).
Start or stop of the watchdog timer after a reset
Selected by the WDTON bit in the OFS register (flash memory).
Initial value of the watchdog timer
Selected by bits WDTUFS0 and WDTUFS1 in the OFS2 register.
Refresh acceptance period for the watchdog timer
Selected by bits WDTRCS0 and WDTRCS1 in the OFS2 register.