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R8C/38T-A Group
7. Voltage Detection Circuit
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 71 of 730
Aug 05, 2011
7.5
Voltage Monitor 1 Interrupt
Set the VW1C1 bit in the VW1C register to 1 (digital filter disabled mode) to use the voltage monitor 1 interrupt to
exit stop mode.
Notes:
1. When the VW1C0 bit is 0, steps 5 and 6 can be performed at the same time (with one instruction).
2. When this setting is made with the voltage monitor 1 interrupt disabled (the VW1C0 bit is 0, the VCA26 bit is 0),
if VCC
Vdet1 (or VCC Vdet1) is detected, no interrupt is generated until the voltage monitor 1 interrupt in
step 11 is enabled. If VCC
Vdet1 (or VCC Vdet1) is detected between steps 9 and 11, the VW1C2 bit is set
to 1. Read the VW1C2 bit after step 11, and perform the processing required for detection if the read value is 1.
Table 7.3
Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt
Step
When Digital Filter is Used
When Digital Filter is Not Used
1
Set bits VD1S0 to VD1S3 in the VD1LS register to select the detection voltage for voltage detection 1.
2
Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled).
3
Wait for td(E-A).
4
Set the IRQ1SEL bit in the CMPA register to select the interrupt type.
5
Set bits VW1F0 and VW1F1 in the VW1C register to
select the sampling clock for the digital filter.
Set the VW1C1 bit in the VW1C register to 1 (digital
filter disabled).
Set the VW1C1 bit in the VW1C register to 0 (digital
filter enabled).
—
7
Set the VCAC1 bit in the VCAC register and the VW1C7 bit in the VW1C register to select the timing for an
interrupt request.
8
Set the VW1C2 bit in the VW1C register to 0.
9
Set the CM14 bit in the CM1 register to 0 (low-speed
on-chip oscillator on).
—
10
Wait for 2 cycles of the sampling clock of the digital
filter.
— (No wait time)
Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt enabled).