APPENDIX A LIST OF I/O REGISTERS
AP-A-4
Seiko Epson Corporation
S1C17651 TECHNICAL MANUAL
0x4240–0x4248
8-bit Timer Ch.0
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T8 Ch.0 Count
Clock Select
Register
(T8_CLK0)
0x4240
(16 bits)
D15–4 –
reserved
–
0 when being read.
D3–0 DF[3:0]
Count clock division ratio select
DF[3:0]
Division ratio
0x0 R/W Source clock = PCLK
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
T8 Ch.0 Reload
Data Register
(T8_TR0)
0x4242
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 TR[7:0]
Reload data
TR7 = MSB
TR0 = LSB
0x0 to 0xff
0x0 R/W
T8 Ch.0
Counter Data
Register
(T8_TC0)
0x4244
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 TC[7:0]
Counter data
TC7 = MSB
TC0 = LSB
0x0 to 0xff
0xff
R
T8 Ch.0
Control Register
(T8_CTL0)
0x4246
(16 bits)
D15–5 –
reserved
–
Do not write 1.
D4
TRMD
Count mode select
1 One shot
0 Repeat
0
R/W
D3–2 –
reserved
–
0 when being read.
D1
PRESER
Timer reset
1 Reset
0 Ignored
0
W
D0
PRUN
Timer run/stop control
1 Run
0 Stop
0
R/W
T8 Ch.0
Interrupt
Control Register
(T8_INT0)
0x4248
(16 bits)
D15–9 –
reserved
–
0 when being read.
D8
T8IE
T8 interrupt enable
1 Enable
0 Disable
0
R/W
D7–1 –
reserved
–
0 when being read.
D0
T8IF
T8 interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
0x4306–0x4314
Interrupt Controller
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Interrupt Level
Setup Register 0
(ITC_LV0)
0x4306
(16 bits)
D15–3 –
reserved
–
0 when being read.
D2–0 ILV0[2:0]
P0 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 1
(ITC_LV1)
0x4308
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV3[2:0]
CT interrupt level
0 to 7
0x0 R/W
D7–0 –
reserved
–
0 when being read.
Interrupt Level
Setup Register 2
(ITC_LV2)
0x430a
(16 bits)
D15–3 –
reserved
–
0 when being read.
D2–0 ILV4[2:0]
RTC interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 3
(ITC_LV3)
0x430c
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV7[2:0]
T16A2 Ch.0 interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV6[2:0]
LCD interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 5
(ITC_LV5)
0x4310
(16 bits)
D15–3 –
reserved
–
0 when being read.
D2–0 ILV10[2:0]
T8 Ch.0 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 6
(ITC_LV6)
0x4312
(16 bits)
D15–3 –
reserved
–
0 when being read.
D2–0 ILV12[2:0]
UART Ch.0 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 7
(ITC_LV7)
0x4314
(16 bits)
D15–3 –
reserved
–
0 when being read.
D2–0 ILV14[2:0]
SPI Ch.0 interrupt level
0 to 7
0x0 R/W
0x4320–0x4326
SPI Ch.0
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
SPI Ch.0
Status Register
(SPI_ST0)
0x4320
(16 bits)
D15–3 –
reserved
–
0 when being read.
D2
SPBSY
Transfer busy flag (master)
1 Busy
0 Idle
0
R
ss signal low flag (slave)
1 ss = L
0 ss = H
D1
SPRBF
Receive data buffer full flag
1 Full
0 Not full
0
R
D0
SPTBE
Transmit data buffer empty flag
1 Empty
0 Not empty
1
R