10 I/O PORTS (P)
10-4
Seiko Epson Corporation
S1C17651 TECHNICAL MANUAL
Interrupt port selection
Select the port generating an interrupt using P0IEy/P0_IMSK register.
Setting P0IEy to 1 enables interrupt generation by the corresponding port. Setting to 0 (default) disables inter-
rupt generation.
Interrupt edge selection
Port input interrupts can be generated at either the rising edge or falling edge of the input signal. Select the edge
used to generate interrupts using P0EDGEy/P0_EDGE register.
Setting P0EDGEy to 1 generates port input interrupts at the input signal falling edge. Setting it to 0 (default)
generates interrupts at the rising edge.
Interrupt flags
The ITC is able to accept one interrupt request from the P0 ports, and the P port module contains interrupt flags
P0IFy/P0_IFLG register corresponding to the individual eight ports to enable individual control of the eight
P0[7:0] port interrupts. P0IFy is set to 1 at the specified edge (rising or falling edge) of the input signal. If the
corresponding P0IEy has been set to 1, an interrupt request signal is also output to the ITC at the same time. An
interrupt is generated if the ITC and S1C17 Core interrupt conditions are satisfied.
P0IFy is reset by writing 1.
For specific information on interrupt processing, see the “Interrupt Controller (ITC)” chapter.
Notes: The P port module interrupt flag P0IFy must be reset in the interrupt handler routine after a
port interrupt has occurred to prevent recurring interrupts.
To prevent generating unnecessary interrupts, reset the relevant P0IFy before enabling inter-
rupts for the required port using P0IEy.
P0 Port Chattering Filter Function
10.6
The P0 ports include a chattering filter circuit for key entry that can be disabled or enabled with a check time speci-
fied individually for the four P0[3:0] and P0[7:4] ports using P0CF1[2:0]/P0_CHAT register and P0CF2[2:0]/P0_
CHAT register, respectively.
6.1 Chattering Filter Function Settings
Table 10.
P0CF1[2:0]/P0CF2[2:0]
Check time *
0x7
16384/fPCLK (8 ms)
0x6
8192/fPCLK (4 ms)
0x5
4096/fPCLK (2 ms)
0x4
2048/fPCLK (1 ms)
0x3
1024/fPCLK (512 s)
0x2
512/fPCLK (256 s)
0x1
256/fPCLK (128 s)
0x0
No check time (off)
(Default: 0x0,
* when PCLK = 2 MHz)
Notes: An unexpected interrupt may occur after SLEEP status is canceled if the slp instruction is
executed while the chattering filter function is enabled. The chattering filter must be disabled
before placing the CPU into SLEEP status.
The chattering filter check time refers to the maximum pulse width that can be filtered.
Generating an input interrupt requires an input time of twice the check time.
The P0 port interrupt must be disabled before setting the P0_CHAT register. Setting the regis-
ter while the interrupt is enabled may generate inadvertent P0 port interrupt. Also the chatter-
ing filter circuit requires a maximum of twice the check time for stabilizing the operation status.
Before enabling the interrupt, make sure that the stabilization time has elapsed.