3 MEMORY MAP, BUS CONTROL
S1C17651 TECHNICAL MANUAL
Seiko Epson Corporation
3-3
Flash Protect Bits
Address
Bit
Function
Setting
Init. R/W
Remarks
0xbffc
(16 bits)
D15–4 reserved
–
D3
Flash write-protect bit for 0xb000–0xbfff
1 Writable
0 Protected
1 R/W
D2
Flash write-protect bit for 0xa000–0xafff
1 Writable
0 Protected
1 R/W
D1
Flash write-protect bit for 0x9000–0x9fff
1 Writable
0 Protected
1 R/W
D0
Flash write-protect bit for 0x8000–0x8fff
1 Writable
0 Protected
1 R/W
0xbffe
(16 bits)
D15–4 reserved
–
D3
Flash data-read-protect bit for 0xb000–0xbfff
1 Readable
0 Protected
1 R/W
D2
Flash data-read-protect bit for 0xa000–0xafff
1 Readable
0 Protected
1 R/W
D1
Flash data-read-protect bit for 0x9000–0x9fff
1 Readable
0 Protected
1 R/W
D0
reserved
1
1 R/W Always set to 1.
Notes: Be sure not to locate the area with data-read protection into the .data and .rodata sections.
Be sure to set D0 of address 0xbffe to 1. If it is set to 0, the program cannot be booted.
Flash Memory Read Wait Cycle Setting
3.2.4
In order to read data from the Flash memory properly, set the appropriate number of wait cycles according to the
system clock frequency using the RDWAIT[1:0]/FLASHC_WAIT register.
FLASHC Read Wait Control Register (FLASHC_WAIT)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
FLASHC Read
Wait Control
Register
(FLASHC_
WAIT)
0x54b0
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7
–
reserved
–
X
–
X when being read.
D6-2 –
reserved
–
0 when being read.
D1–0 RDWAIT
[1:0]
Flash read wait cycle
RDWAIT[1:0]
Wait
0x3 R/W
0x3
0x2
0x1
0x0
3 wait
2 wait
1 wait
No wait
D[1:0]
RDWAIT[1:0]: Flash Read Wait Cycle Bits
Sets the number of wait cycles for reading from the Flash memory. One wait insertion prolongs bus
cycles by one system clock cycle.
Note: Set RDWAIT[1:0] to 0x0 to achieve the best performance.
Internal RAM Area
3.3
Embedded RAM
3.3.1
The S1C17651 contains a RAM in the 2K-byte area from address 0x0 to address 0x7ff. The RAM allows high-
speed execution of the instruction codes copied into it as well as storing variables and other data.
Note: The 64-byte area at the end of the RAM (0x7c0–0x7ff) is reserved for the on-chip debugger. When
using the debug functions under application development, do not access this area from the appli-
cation program.
This area can be used for applications of mass-produced devices that do not need debugging.
The S1C17651 enables the RAM size used to apply restrictions to 2KB, 1KB, or 512B. For example, when using
the S1C17651 to develop an application for a built-in ROM model, you can set the RAM size to match that of the
target model, preventing creating programs that seek to access areas outside the RAM areas of the target product.
The RAM size is selected using IRAMSZ[2:0]/MISC_IRAMSZ register.