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| 型号： | S1C17651B00E10M |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 2 MHz, RISC MICROCONTROLLER, PBGA |
| 文件页数： | 148/216页 |
| 文件大小： | 1784K |
| 代理商： | S1C17651B00E10M |
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6 INTERRUPT CONTROLLER (ITC)
6-4
Seiko Epson Corporation
S1C17651 TECHNICAL MANUAL
3.2.1 Interrupt Level Setting Bits
Table 6.
Hardware interrupt
Interrupt level setting bits
Register address
P0 port interrupt
ILV0[2:0] (D[2:0]/ITC_LV0 register)
0x4306
Clock timer interrupt
ILV3[2:0] (D[10:8]/ITC_LV1 register)
0x4308
RTC interrupt
ILV4[2:0] (D[2:0]/ITC_LV2 register)
0x430a
LCD interrupt
ILV6[2:0] (D[2:0]/ITC_LV3 register)
0x430c
16-bit PWM timer Ch.0 interrupt
ILV7[2:0] (D[10:8]/ITC_LV3 register)
0x430c
8-bit timer Ch.0 interrupt
ILV10[2:0] (D[2:0]/ITC_LV5 register)
0x4310
UART Ch.0 interrupt
ILV12[2:0] (D[2:0]/ITC_LV6 register)
0x4312
SPI Ch.0 interrupt
ILV14[2:0] (D[2:0]/ITC_LV7 register)
0x4314
Interrupt Processing by the S1C17 Core
6.3.3
A maskable interrupt to the S1C17 Core occurs when all of the following conditions are met:
The interrupt is enabled by the interrupt control bit inside the peripheral module.
The IE (Interrupt Enable) bit of the PSR (Processor Status Register) in the S1C17 Core has been set to 1.
The cause of interrupt that has occurred has a higher interrupt level than the value set in the IL field of the PSR.
No other cause of interrupt having higher priority, such as NMI, has occurred.
If an interrupt cause that has been enabled in the peripheral module occurs, the corresponding interrupt flag is set to 1,
and this state is maintained until it is reset by the program. This means that the interrupt cause is not cleared even if
the conditions listed above are not met when the interrupt cause occurs. An interrupt occurs if the above conditions
are met.
If multiple maskable interrupt causes occurs simultaneously, the interrupt cause with the highest interrupt level and
lowest vector number becomes the subject of the interrupt request to the S1C17 Core. Interrupts with lower levels
are held until the above conditions are subsequently met.
The S1C17 Core samples interrupt requests for each cycle. On accepting an interrupt request, the S1C17 Core
switches to interrupt processing immediately after execution of the current instruction has been completed.
Interrupt processing involves the following steps:
(1) The PSR and current program counter (PC) values are saved to the stack.
(2) The PSR IE bit is reset to 0 (disabling subsequent maskable interrupts).
(3) The PSR IL bits are set to the received interrupt level. (The NMI does not affect the IL bits.)
(4) The vector for the interrupt occurred is loaded to the PC to execute the interrupt handler routine.
When an interrupt is accepted, (2) prevents subsequent maskable interrupts. Setting the IE bit to 1 in the interrupt
handler routine allows handling of multiple interrupts. In this case, since IL is changed by (3), only an interrupt
with a higher level than that of the currently processed interrupt will be accepted.
Ending interrupt handler routines using the reti instruction returns the PSR to the state before the interrupt has
occurred. The program resumes processing following the instruction being executed at the time the interrupt oc-
curred.
NMI
6.4
In the S1C17651, the watchdog timer can generate a non-maskable interrupt (NMI). The vector number for NMI is 2,
with the vector address set to the vector table's starting address + 8 bytes.
This interrupt takes precedence over other interrupts and is unconditionally accepted by the S1C17 Core.
For detailed information on generating NMI, see the “Watchdog Timer (WDT)” chapter.
Software Interrupts
6.5
The S1C17 Core provides the “int imm5” and “intl imm5,imm3” instructions allowing the software to gener-
ate any interrupts. The operand imm5 specifies a vector number (0–31) in the vector table. In addition to this, the
intl instruction has the operand imm3 to specify the interrupt level (0–7) to be set to the IL field in the PSR.
The processor performs the same interrupt processing as that of the hardware interrupt.
相关PDF资料 |
PDF描述 |
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| S1C17651F00E10B | 16-BIT, FLASH, 2 MHz, RISC MICROCONTROLLER, PQFP64 |
| S1C17701F00E100 | MICROCONTROLLER, PQFP144 |
| S1C17711F00E10C | 16-BIT, FLASH, RISC MICROCONTROLLER, PQFP128 |
| S1C17711B00E10K | 16-BIT, FLASH, RISC MICROCONTROLLER, PBGA144 |
| S1C17711B00E10N | 16-BIT, FLASH, RISC MICROCONTROLLER, PBGA144 |
相关代理商/技术参数 |
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| S1C17653 | 制造商:EPSON 制造商全称:EPSON 功能描述:16-bit Single Chip Microcontroller |
| S1C17701 | 制造商:EPSON 制造商全称:EPSON 功能描述:CMOS 16-bit Single Chip Microcontroller |
| S1C17701D101000 | 制造商:Seiko Instruments Inc (SII) 功能描述:EPSON 16BIT MCU |
| S1C17701F00B100 | 功能描述:16位微控制器 - MCU 16-bit 64KB Flash LCD 56x32 RoHS:否 制造商:Texas Instruments 核心:RISC 处理器系列:MSP430FR572x 数据总线宽度:16 bit 最大时钟频率:24 MHz 程序存储器大小:8 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:VQFN-40 安装风格:SMD/SMT |
| S1C17701F00E100 | 功能描述:16位微控制器 - MCU 16-bit 64KB Flash LCD 56x32 RoHS:否 制造商:Texas Instruments 核心:RISC 处理器系列:MSP430FR572x 数据总线宽度:16 bit 最大时钟频率:24 MHz 程序存储器大小:8 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:VQFN-40 安装风格:SMD/SMT |
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