15 UART
S1C17651 TECHNICAL MANUAL
Seiko Epson Corporation
15-13
D3
PREN: Parity Enable Bit
Enables the parity function.
1 (R/W): With parity
0 (R/W): No parity (default)
PREN is used to select whether received data parity checking is performed and whether a parity bit is
added to transmit data. Setting PREN to 1 parity-checks the received data. A parity bit is automatically
added to the transmit data. If PREN is set to 0, no parity bit is checked or added.
D2
PMD: Parity Mode Select Bit
Selects the parity mode.
1 (R/W): Odd parity
0 (R/W): Even parity (default)
Writing 1 to PMD selects odd parity; writing 0 to it selects even parity. Parity checking and parity bit
addition are enabled only when PREN is set to 1. The PMD setting is disabled if PREN is 0.
D1
STPB: Stop Bit Select Bit
Selects the stop bit length.
1 (R/W): 2 bits
0 (R/W): 1 bit (default)
Writing 1 to STPB selects 2 stop bits; writing 0 to it selects 1 bit. The start bit is fixed at 1 bit.
D0
Reserved
UART Ch.x Control Register (UART_CTLx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
UART Ch.x
Control Register
(UART_CTLx)
0x4104
(8 bits)
D7
TEIEN
End of transmission int. enable
1 Enable
0 Disable
0
R/W
D6
REIEN
Receive error int. enable
1 Enable
0 Disable
0
R/W
D5
RIEN
Receive buffer full int. enable
1 Enable
0 Disable
0
R/W
D4
TIEN
Transmit buffer empty int. enable
1 Enable
0 Disable
0
R/W
D3–2 –
reserved
–
0 when being read.
D1
RBFI
Receive buffer full int. condition setup 1 2 bytes
0 1 byte
0
R/W
D0
RXEN
UART enable
1 Enable
0 Disable
0
R/W
D7
TEIEN: End of Transmission Interrupt Enable Bit
Enables interrupt requests to the ITC when transmit operation has completed.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set this bit to 1 to terminate transmit processing using interrupts.
D6
REIEN: Receive Error Interrupt Enable Bit
Enables interrupt requests to the ITC when a receive error occurs.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set this bit to 1 to process receive errors using interrupts.
D5
RIEN: Receive Buffer Full Interrupt Enable Bit
Enables interrupt requests to the ITC caused when the received data quantity in the receive data buffer
reaches the quantity specified in RBFI.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set this bit to 1 to read received data using interrupts.
D4
TIEN: Transmit Buffer Empty Interrupt Enable Bit
Enables interrupt requests to the ITC caused when transmission data in the transmit data buffer is sent
to the shift register (i.e. when data transmission begins).
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set this bit to 1 to write data to the transmit data buffer using interrupts.