20 ON-CHIP DEBUGGER (DBG)
20-4
Seiko Epson Corporation
S1C17651 TECHNICAL MANUAL
4.2 Internal RAM Size Selection
Table 20.
IRAMSZ[2:0]
Internal RAM size
0x5
512B
0x4
1KB
0x3
2KB
Other
Reserved
(Default: 0x3)
Note: The MISC_IRAMSZ register is write-protected. To alter this register settings, you must override
this write-protection by writing 0x96 to the MISC_PROT register. Normally, the MISC_PROT reg-
ister should be set to a value other than 0x96, except when altering the MISC_IRAMSZ register.
Unnecessary rewriting of the MISC_IRAMSZ register may result in system malfunctions.
Debug RAM Base Register (DBRAM)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Debug RAM
Base Register
(DBRAM)
0xffff90
(32 bits)
D31–24 –
Unused (fixed at 0)
0x0
R
D23–0 DBRAM[23:0] Debug RAM base address
0x7c0
0x7c0 R
D[31:24] Not used (Fixed at 0)
D[23:0]
DBRAM[23:0]: Debug RAM Base Address Bits
Read-only register containing the beginning address of the debugging work area (64 bytes).
Debug Control Register (DCR)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Debug Control
Register
(DCR)
0xffffa0
(8 bits)
D7
IBE4
Instruction break #4 enable
1 Enable
0 Disable
0
R/W
D6
IBE3
Instruction break #3 enable
1 Enable
0 Disable
0
R/W
D5
IBE2
Instruction break #2 enable
1 Enable
0 Disable
0
R/W
D4
DR
Debug request flag
1 Occurred
0 Not occurred
0
R/W Reset by writing 1.
D3
IBE1
Instruction break #1 enable
1 Enable
0 Disable
0
R/W
D2
IBE0
Instruction break #0 enable
1 Enable
0 Disable
0
R/W
D1
SE
Single step enable
1 Enable
0 Disable
0
R/W
D0
DM
Debug mode
1 Debug mode 0 User mode
0
R
D7
IBE4: Instruction Break #4 Enable Bit
Enables or disables instruction break #4.
1 (R/W): Enabled
0 (R/W): Disabled (default)
If this bit is set to 1, the instruction fetch address and the value set in the IBAR4 register are compared.
If they match, an instruction break is generated. If this bit is set to 0, no comparison is performed.
D6
IBE3: Instruction Break #3 Enable Bit
Enables or disables instruction break #3.
1 (R/W): Enabled
0 (R/W): Disabled (default)
If this bit is set to 1, the instruction fetch address and the value set in the IBAR3 register are compared.
If they match, an instruction break is generated. If this bit is set to 0, no comparison is performed.
D5
IBE2: Instruction Break #2 Enable Bit
Enables or disables instruction break #2.
1 (R/W): Enabled
0 (R/W): Disabled (default)
If this bit is set to 1, the instruction fetch address and the value set in the IBAR2 register are compared.
If they match, an instruction break is generated. If this bit is set to 0, no comparison is performed.