1 OVERVIEW
S1C17651 TECHNICAL MANUAL
Seiko Epson Corporation
1-5
Pin Descriptions
1.3.2
Note: The pin names described in boldface type are default settings.
3.2.1 Pin Descriptions
Table 1.
Pin No.
Name
I/O
Default
status
Function
Chip
TQFP
20–1
23–17, 15–3 SEG0–
SEG19
O
O (Hi-Z)
LCD segment output pins
24–21
27–24
COM0–
COM3
O
O (Hi-Z)
LCD common output pins
25
28
VC3
–
LCD system power supply circuit output pin
26
29
VC2
–
LCD system power supply circuit output pin
27
30
VC1
–
LCD system power supply circuit output pin
28
31
CB
–
Voltage boost capacitor connecting pin for LCD system power supply circuit
29
32
CA
–
Voltage boost capacitor connecting pin for LCD system power supply circuit
30
36
IREF_M
–
IREF constant current monitor pin
(Leave the pin open during normal operation.)
31
37
VOSC
–
Oscillation system voltage regulator output pin
32
38
OSC1
I
OSC1A oscillation input pin
33
39
OSC2
O
OSC1A oscillation output pin
34
40
VD1
–
Internal logic system voltage regulator output pin
35
41
OSC3
I
OSC3A oscillation input pin
36
42
OSC4
O
OSC3A oscillation output pin
37
43
TEST0
I I (Pull-down) Test input pin (Connect to VSS for normal operation.)
38
44
VSS
–
GND pin
39
45
VDD
–
Power supply pin (2.0 to 3.6 V)
40
46
#RESET
I
I (Pull-up) Initial reset input pin
41
49
P00
I/O I (Pull-up) I/O port pin (with port input interrupt function)
SIN0 I
UART Ch.0 data input pin
42
50
P01
I/O I (Pull-up) I/O port pin (with port input interrupt function)
SOUT0 O
UART Ch.0 data output pin
43
51
P02
I/O I (Pull-up) I/O port pin (with port input interrupt function)
SCLK0 I
UART Ch.0 external clock input pin
FOUTA O
Clock output pin
REGMON O
Theoretical regulation clock monitor output pin
44
52
P03
I/O I (Pull-up) I/O port pin (with port input interrupt function)
EXCL0 I
T16A2 Ch.0 external clock input pin
REGMON O
Theoretical regulation clock monitor output pin
LFRO O
LCD frame signal output pin
45
53
P04
I/O I (Pull-up) I/O port pin (with port input interrupt function)
TOUTA0 O
T16A2 Ch.0 TOUT A signal output pin
CAPA0 I
T16A2 Ch.0 capture A trigger signal input pin
46
54
P05
I/O I (Pull-up) I/O port pin (with port input interrupt function)
TOUTB0 O
T16A2 Ch.0 TOUT B signal output pin
CAPB0 I
T16A2 Ch.0 capture B trigger signal input pin
#SPISS0 I
SPI Ch.0 slave select signal input pin
47
55
P06
I/O I (Pull-up) I/O port pin (with port input interrupt function)
BZ O
Buzzer output pin
SDI0 I
SPI Ch.0 data input pin
48
56
P07
I/O I (Pull-up) I/O port pin (with port input interrupt function)
#BZ O
Buzzer inverted output pin
SDO0 O
SPI Ch.0 data output pin
49
57
P10
I/O I (Pull-up) I/O port pin
FOUTB O
Clock output pin
SPICLK0 I/O
SPI Ch.0 clock input/output pin
50
58
DCLK
O
O (H)
On-chip debugger clock output pin
P11 I/O
I/O port pin
BZ O
Buzzer output pin
51
59
DSIO
I/O I (Pull-up) On-chip debugger data input/output pin
P12 I/O
I/O port pin
#BZ O
Buzzer inverted output pin
52
60
DST2
O
O (L)
On-chip debugger status output pin
P13 I/O
I/O port pin
53
61
VDD
–
Power supply pin (2.0 to 3.6 V)
54
62
VSS
–
GND pin
55
63
VPP
–
Flash programming/erasing power supply pin (7.0/7.5 V)
(Leave the pin open during normal operation.)