17 LCD DRIVER (LCD)
S1C17651 TECHNICAL MANUAL
Seiko Epson Corporation
17-11
For normal display, set DSPC[1:0] to 0x1. Note that the clock must be supplied. (See Section 17.3.)
If “Display off” is selected, the drive voltage supplied from the LCD power supply circuit stops, and the
VC1 to VC3 pins are all set to VSS level.
Since “All on” and “All off” directly control the driving waveform output by the LCD driver, display
memory data is not altered. COM pins are set to dynamic drive for “All on” and to static drive for “All
off.” This function can be used to make the display flash on and off without altering the display memo-
ry.
DSPC[1:0] is reset to 0x0 (Display off) after an initial reset. DSPC[1:0] is also reset to 0x0 when the
slp instruction is executed and it reverts to the previous setting after SLEEP mode is canceled.
LCD Clock Control Register (LCD_CCTL)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
LCD Clock
Control Register
(LCD_CCTL)
0x50a2
(8 bits)
D7–6 FRMCNT[1:0] Frame frequency control
FRMCNT[1:0] Division ratio
0x1 R/W Source clock: LCLK
0x3
0x2
0x1
0x0
1/16
1/12
1/8
1/4
D5–3 –
reserved
–
0 when being read.
D2–0 LDUTY[2:0] LCD duty select
LDUTY[2:0]
Duty
0x3 R/W
0x7–0x4
0x3
0x2
0x1
0x0
reserved
1/4
1/3
1/2
Static
D[7:6]
FRMCNT[1:0]: Frame Frequency Control Bits
Sets the Frame frequency.
8.5 Frame Frequency Settings (when the clock source is OSC1 = 32.768 kHz (LCLK = 512 Hz))
Table 17.
Drive duty
(LDUTY[2:0] setting)
FRMCNT[1:0] setting (LCLK division ratio)
0x0
0x1
0x2
0x3
1/4 duty (0x3)
128 Hz (1/4)
64 Hz (1/8) *
42.67 Hz (1/12)
32 Hz (1/16)
1/3 duty (0x2)
85.33 Hz (1/6)
56.89 Hz (1/9)
42.67 Hz (1/12)
34.13 Hz (1/15)
1/2 duty (0x1)
128 Hz (1/4)
64 Hz (1/8)
42.67 Hz (1/12)
32 Hz (1/16)
Static (0x0)
128 Hz (1/4)
64 Hz (1/8)
42.67 Hz (1/12)
32 Hz (1/16)
* Default setting
8.6 Frame Frequency Settings (when the clock source is OSC3B/OSC3A)
Table 17.
Drive duty
(LDUTY[2:0] setting)
FRMCNT[1:0] setting
0x0
0x1
0x2
0x3
1/4 duty (0x3)
fOSC3
× LCDTCLKD
––––––––––––––––
4
fOSC3
× LCDTCLKD *
––––––––––––––––
8
fOSC3
× LCDTCLKD
––––––––––––––––
12
fOSC3
× LCDTCLKD
––––––––––––––––
16
1/3 duty (0x2)
fOSC3
× LCDTCLKD
––––––––––––––––
6
fOSC3
× LCDTCLKD
––––––––––––––––
9
fOSC3
× LCDTCLKD
––––––––––––––––
12
fOSC3
× LCDTCLKD
––––––––––––––––
15
1/2 duty (0x1)
fOSC3
× LCDTCLKD
––––––––––––––––
4
fOSC3
× LCDTCLKD
––––––––––––––––
8
fOSC3
× LCDTCLKD
––––––––––––––––
12
fOSC3
× LCDTCLKD
––––––––––––––––
16
Static (0x0)
fOSC3
× LCDTCLKD
––––––––––––––––
4
fOSC3
× LCDTCLKD
––––––––––––––––
8
fOSC3
× LCDTCLKD
––––––––––––––––
12
fOSC3
× LCDTCLKD
––––––––––––––––
16
* Default setting
fOSC3: OSC3B or OSC3A clock frequency
LCDTCLKD: OSC3B/OSC3A division ratio (1/1024 to 1/8192)
D[5:3]
Reserved