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参数资料
型号： S1R72803F00A100
元件分类： 微控制器/微处理器
英文描述： 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100
封装： 0.40 MM PITCH, PLASTIC, QFP20-184
文件页数： 59/115页
文件大小： 833K
代理商： S1R72803F00A100
S1R72803F00A
44
EPSON
Address Register Name
Bit Symbol
R/W
Description
H.Rst S.Rst B.Rst
0x03
DmaIntStat
7:
0:
1:
6: TxAsyRtyGo
R(W)
0: None
1: Async Tx Retry Go
5: TxAsyBCSent R(W)
0: None
1: AsyncTxBroadcast Sent
4: RxDmaFaild
R(W)
0: None
1: Rx DMA Failed
0x00
–
3: TxAsyFaild
R(W)
0: None
1: Async Tx Failed
2: TxIsoFaild
R(W)
0: None
1: ISO Tx Failed
1: TxAsyBRAbort R(W)
0: None
1: Async Tx BusReset Abort
0: TxAsyMiss
R(W)
0: None
1: AsyncTxAckCodeMissing
DMA Interrupt Status Register
The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become
“H” when the associated bit of the DMAIntEnb Register is “1”, this register asserts the interrupt signal to the
CPU.
The CPU reads this register after receiving the interrupt signal to locate an interrupt source. By writing the read
value again, it clears these bits.
Bit7 Reserved
When a Sub Action Gap is detected in PHY status of PHY/LINK interface, this bit becomes “1”.
Bit6 Transmit Async Packet Retry Go
When an auto retry is performed after transmitting an Async packet and receiving an Ack_busy, this bit becomes
“1”.
Bit5 Transmit Async Broadcast Packet Sent
After a transmission of a Broadcast packet of Async or a PHY packet finishes, this bit becomes “1”.
Bit4 Receive Packet LINK DMA Failed
When a received packet cannot be written to the buffer due to the following reasons, this bit becomes “1”.
1) DMA was too late.
2) A packet was received when the ForceBusy bit is on.
Bit3 Transmit Async Packet LINKDMA Failed
When data cannot be transferred from the buffer to the LINK core at the time of Async packet transmission
(DMA FIFO is Under Flow), this bit becomes “1”.
Bit2 Transmit ISO Packet LINKDMA Failed
When data cannot be transferred from the buffer to the LINK core at the time of ISO packet transmission (DMA
FIFO is Under Flow), this bit becomes “1”.
Bit 1 Transmit Async Packet BusReset Abort
When a Transmit packet is disabled by a BusReset before an Ack packet is returned at the time of Async packet
transmission, this bit becomes “1”.
Bit0 Transmit Async Packet Ack-code Missing
When a Ack packet is not returned at the time of Async packet transmission, this bit becomes “1”.
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