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参数资料
型号： S1R72803F00A100
元件分类： 微控制器/微处理器
英文描述： 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100
封装： 0.40 MM PITCH, PLASTIC, QFP20-184
文件页数： 91/115页
文件大小： 833K
代理商： S1R72803F00A100
S1R72803F00A
EPSON
73
Address Register Name
Bit Symbol
R/W
Description
H.Rst S.Rst B.Rst
0x52
AsyDmaCtl
7: AsyChnlSel
R/W 0: AsyTxPktHdr0
1: AsyTxPktHdr1
6:
0:
1:
5:
0:
1:
4: BlkWrAreaSel R/W 0: Rx ORB Area
1: Rx Stream Area
0x00
–
3: AsyFIFOEpty
R
0: AsyFIFO Empty
1: Non Empty
2: AsyFIFOClr
W
0: Normal
1: AsyFIFO Clear
1: AsyTxMon
R
0: Async Tx Stop
1: Async Tx Run
0: AsyStart
W
0: normal
1: Async Start
Async TxDMA Control Register
Bit7 Async Transmit Packet Header Channel Select
Selects the header area of an Async Transmit packet from DMA. You transmit send a transmit packet from the
selected area. This bit selects “0”: AsyncTxPktHdr0 or “1”: AsyncTxPktHdr1. Since the AsyncTxPktHdr1 area
overlaps the ISOTxPktHdr area, however, the firmware must decide how to use this area.
Bit6 Reserved
Bit5 Reserved
Bit4 Block Write Request Packet Data Area Select
Can divide the store area of the Block Write Request packet data between the RxORBArea and RxStreamArea.
o:RxORBArea
1:RxStreamArea
Bit3 Async FIFO Empty
When the DMA-FIFO for Async is empty, this bit becomes “0”. When it is not empty, it is “1”. This bit is read-
only and writing to this bit is ignored.
Bit2 Async FIFO Clear
Clears the DMA-FIFO for Async. Writing “1” to this bit clears the FIFO. After clearing it, this bit is
automatically restored to “0”.
Bit1 Async Transmit Monitor
Indicates the transmit status of Async. “1” indicates that an Async packet is in transmission and “0” indicates
that no Async packet is in transmission. This bit is read-only and writing to this bit is ignored.
Bit0 Async Transmit Start
Transmits an Async packet. Writing “1” to this bit starts to transmit an Async packet. On completion of the
transmission, it is automatically restored to “0”. If you read this bit, it always indicates “0” regardless of
presence/absence of transmit.
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