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参数资料
型号： S1R72803F00A100
元件分类： 微控制器/微处理器
英文描述： 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100
封装： 0.40 MM PITCH, PLASTIC, QFP20-184
文件页数： 79/115页
文件大小： 833K
代理商： S1R72803F00A100
S1R72803F00A
62
EPSON
Address Register Name
Bit Symbol
R/W
Description
H.Rst S.Rst B.Rst
0x32
SBP2IntStat
7: SplitTimeOut
R(W)
0: None
1: SplitTimeOut
6: TxAckedIllegal R(W)
0: None
1: TxAckedIllegal
5: TxAckMiss
R(W)
0: None
1: TxAsyMiss
4: BrAbort
R(W)
0: None
1: BrAbort
0x00
–
3: NotQuad
R(W)
0: None
1: NotQuad
2: RxNotRespCmp R(W)
0: None
1: RxNotRespCmp
1: RxBroadCast
R(W)
0: None
1: RxBroadCast
0: RxAckDataErr
R(W)
0: None
1: RxAckDataErr
Hardware SBP2 Interrupt Status Register
This register indicates error information when an error arises in execution of the hardware SBP2 processing.
At the same time, it asserts the HwSBP2Err bit of the SubIntStat Register. When clearing it, write “1” to a bit
to clear.
This register is automatically cleared when setting HwSBP2Ctl.HwSBP2Start or the HWSBP2Ctl. HwSBP2Rst.
Bit7 Split Timeout
SplitTimeOut:1 => During the HwSBP2 processing, an SPLIT TIMEOUT error arose.
Bit6 Tx Acked Illegal
TxAckedIllegal:1 => Though a transmission was completed, a response other than ack_pending was given to
a BlkRdReq and a response other than ack_completed was given to a BlkWrReq.
Bit5 Tx Ack Miss
TxAsyMiss:1 => Though a transmission was completed, no Ack was returned.
Bit4 BRAbort
When the HwSBP2Ctl.HwSBP2Start bit is set to “1” or HWSBP2Ctl.Resume bit is set to “1” during the
BusReset period, this bit becomes “1”,
Bit3 NotQuad
This bit indicates 1 if SegmentLength of PageTableElement is not the Quad unit during the HwSBP2 process.
No data transmission to the detected PageTableElement occurs.
This bit is cleared when 1 is written.
This bit is automatically cleared when a Transaction starts or SBP2Reset is issued.
Bit2 RxNotRespCmp
RxNotRespCmp:1 => Though a response packet receive was completed, its code was other than resp_complete.
Bit1 RxBroadcast
RxBroadCast:1 => Though a response packet receive was completed, it was a broadcast packet.
Bit0 RxAckDataError
RxAckDataErr:1 => Though a response packet was received, it was a DataCRCError. It does not assert the
interrupt signal SBP2Err. It is automatically cleared on completion of the Transaction.
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