参数资料
型号: S1R72803F00A100
元件分类: 微控制器/微处理器
英文描述: 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100
封装: 0.40 MM PITCH, PLASTIC, QFP20-184
文件页数: 93/115页
文件大小: 833K
代理商: S1R72803F00A100
S1R72803F00A
EPSON
75
Address Register Name
Bit Symbol
R/W
Description
H.Rst S.Rst B.Rst
0x54
RxDmaCtl
7:
0:
1:
6:
0:
1:
5:
0:
1:
4:
0:
1:
0x00
3: RxFIFOEpty
R
0: Rx FIFO Empty
1: Non Empty
2: RxFIFOClr
W
0: Normal
1: Rx FIFO Clear
1: RxMon
R
0: Rx Stop
1: Rx Run
0: ForceBusy
R/W
0: Normal
1: Busy
Rx DMA Control Register
Bit7..4 Reserved
Bit3 Receive FIFO Empty
When the DMA-FIFO for reception is empty, this bit becomes “0”. When it is not empty, it is “1”. This bit is
read-only and writing to this bit is ignored.
Bit2 Receive FIFO Clear
Clears the DMA-FIFO for reception. Writing “1” to this bit clears the FIFO. After clearing it, this bit is
automatically restored to “0”.
Bit1 Reception Monitor
Indicates the receive status of ISO. “1” indicates that a receive packet is in reception and “0” indicates that no
receive packet is in reception. This bit is read-only and writing to this bit is ignored.
Bit0 Force Busy
Setting this bit to “1” can forcedly return an Ack_Busy to a receive packet.
Before performing the RxData Clear or RxHdrClear, be sure to set this bit.
If you set this bit during receiving a packet, the packet operates to complete the reception regardless of to what
extent the packet has been received. It means that a RxDmaCmp interrupt occurs if this packet has been correctly
received. The Ack_busy is continuously returned to the subsequent receive packets.
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