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参数资料
| 型号： | S29JL032H60TAI023 |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | PROM |
| 英文描述： | 2M X 16 FLASH 3V PROM, 60 ns, PDSO48 |
| 封装： | MO-142DD, TSOP-48 |
| 文件页数： | 22/66页 |
| 文件大小： | 1691K |
| 代理商： | S29JL032H60TAI023 |
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March 10, 2005 S29JL032H_00A11
S29JL032H
27
Ad vance
Info rmat i o n
The SecSi Sector area can be protected using one of the following procedures:
Write the three-cycle Enter SecSi Sector Region command sequence, and
then follow the in-system sector protect algorithm as shown in Figure 2. This
allows in-system protection of the SecSi Sector Region without raising any
device pin to a high voltage. Note that this method is only applicable to the
SecSi Sector.
Write the three-cycle Enter SecSi Sector Region command sequence, and
then use the alternate method of sector protection described in the “Sector/
Sector Block Protection and Unprotection” section.
Once the SecSi Sector is locked and verified, the system must write the Exit SecSi
Sector Region command sequence to return to reading and writing the remainder
of the array.
The SecSi Sector lock must be used with caution since, once locked, there is no
procedure available for unlocking the SecSi Sector area and none of the bits in
the SecSi Sector memory space can be modified in any way.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to Table 13 for com-
mand definitions). In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might otherwise be caused by
spurious system level signals during VCC power-up and power-down transitions,
or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This pro-
tects data during VCC power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to the read
mode. Subsequent writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control pins to prevent unintentional writes
when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# =
VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families. Flash vendors can
standardize their existing interfaces for long-term compatibility.
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