List of Instruction Descriptions
Instruction
Full Register Name
Page
Mnemonic
Number
ADC (1)
Add with Carry Register ............................................................................................. 6-21
ADC (2)
Add with Carry Immediate .......................................................................................... 6-22
ADD (1)
Add Register............................................................................................................... 6-23
ADD (2)
Add Small Immediate ................................................................................................. 6-24
ADD (3)
Add Immediate ........................................................................................................... 6-25
ADD (4)
Add Extended Register .............................................................................................. 6-26
ADD (5)
Add Immediate to extended Register......................................................................... 6-27
ADD (6)
Add 5-bit Immediate to extended Register................................................................. 6-28
AND (1)
AND Register ............................................................................................................. 6-29
AND (1)
AND Small Immediate ................................................................................................ 6-30
AND (2)
AND Large Immediate................................................................................................ 6-31
BITop
BIT Operation ............................................................................................................. 6-32
BNZD
Branch Not Zero with Auto decrement ....................................................................... 6-33
BR
Conditional Branch ..................................................................................................... 6-34
BRA EC
Branch on External Condition .................................................................................... 6-35
BREAK
Break .......................................................................................................................... 6-36
BSRD
Branch Subroutine with Delay Slot............................................................................. 6-37
CLD
Coprocessor Load ...................................................................................................... 6-38
CLRSR
Clear SR ..................................................................................................................... 6-39
CMP (1)
Compare Register ...................................................................................................... 6-40
CMP (2)
Compare Immediate................................................................................................... 6-41
CMP (3)
Compare Short Immediate ......................................................................................... 6-42
CMPEQ (1)
Compare Equal Extended Register............................................................................ 6-43
CMPEQ (2)
Compare Equal Small Immediate .............................................................................. 6-44
CMPEQ (3)
Compare Equal Large Immediate .............................................................................. 6-45
COM
Complement ............................................................................................................... 6-46
COP
Coprocessor ............................................................................................................... 6-47
DECC
Decrement with Carry................................................................................................. 6-48
DT
Decrement and Test................................................................................................... 6-49
EXT
Sign-Extend ................................................................................................................ 6-50
S3CC40D/FC40D_UM_REV1.20 MICROCONTROLLER
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