S3CC40D/FC40D_UM_REV1.20
16-BIT TIMER 3
Programmable Pulse Generate Mode
Programmable Pulse Generate (PPG) mode lets you program the width (duration) of the pulse that is output at
the T3PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the
value written to the Timer 3 data register. In PPG mode, however, the match signal does not clear the counter but
can generate a match interrupt. The counter runs continuously, next timer 3 data register, and then repeats the
incrementing from 0000H. When matched with the T3ADATAH/L and T3BDATAH/L Registers next time, the timer
output is inverted again.
Although you can use the match interrupt in PPG mode, interrupt is not typically used in PPG-type applications.
Instead, the pulse at the T3PWM pin is held to Low level as long as the reference data value (T3ADATAH/L) is
less than (
< ) the counter value, and then the pulse is held to High level for as long as the reference data value
(T3BDATAH/L) is less than (
< ) the counter value. The counter runs Timer 3 Data Buffer Register value. So, the
first time, you should set T3CONH.1 to “1” after data are loaded to T3ADATAH/L and T3BDATAH/L.
External Clock Edge Mode
In external clock edge mode, a match signal is generated and T3OUT is toggled when the counter value is
identical to the value written to the T3 reference data register, T3ADATAH/L. The match signal generates a Timer
3 match interrupt (T3INT) and clears the counter.
In this mode, counting is started by an external clock. This clock is the edge of the T3CLK pin input. Either the
rising or falling edge can be selected with T3CONL.7. Source clock is an internal clock. The contents of
T3ADATAH/L is compared with the contents of counter. If a match is found, an T3INT interrupt request is
generated, and the counter is cleared to “0”. The counter is restarted by the selected edge of the T3CLK pin input.
External clock edge start mode, the reverse directive edge input is ignored. The T3CLK pin input edge before a
match detection is also ignored.
External clock edge start/stop mode, inputting the edge to the reverse direction of the clock edge to start counting
stop the counter. Inputting a constant pulse width can start continuously counting the counter and generate
interrupts.
External clock edge start/clear mode, inputting the edge to the reverse direction of the clock edge to start
counting clears the counter, and the counter is stopped. Inputting a constant pulse width can generate interrupts.
External clock edge start/restart mode, inputting the edge to the reverse direction of the clock edge to start
counting clears the counter, and the counter is restart. Inputting a constant pulse width can also start counting
clears the counter, and the counter is restart. Either the reverse direction of the clock edge or a constant pulse
width can generate interrupts.
15-3