16-BIT TIMER 5
S3CC40D/FC40D_UM_REV1.20
FUNCTION DESCRIPTION
Timer 5 Interrupts (IRR18, IRR19)
The Timer 5 module can generate two interrupts: the Timer 5 overflow interrupt (T5OVF), and the Timer 5 match/
capture interrupt (T5INT). T5OVF is interrupt level IRR19. T5INT belongs to interrupt level IRR18.
Interval Timer Function
The Timer 5 module can generate an interrupt: the Timer 5 match interrupt (T5INT).
In interval timer mode, a match signal is generated and T5OUT is toggled when the counter value is identical to
the value written to the T5 reference data register, T5DATAH/L. The match signal generates a Timer 5 match
interrupt (T5INT) and clears the counter.
If, for example, you write the value 1087H to T5DATAH/L and 03H to T5CON, the counter will increment until it
reaches 1087H. At this point, the T5 interrupt request is generated, the counter value is reset, and counting
resumes.
Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
T5PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the
value written to the Timer 5 data register. In PWM mode, however, the match signal does not clear the counter
but can generate a match interrupt. The counter runs continuously, overflowing at FFFFH, and then repeats the
incrementing from 0000H. Whenever an overflow occurs, an overflow (OVF) interrupt can be generated.
Although you can use the match or the overflow interrupt in PWM mode, interrupts are not typically used in PWM-
type applications. Instead, the pulse at the T5PWM pin is held to High level as long as the reference data value is
less than or equal to (
≤ ) the counter value, and then the pulse is held to Low level for as long as the data value
is greater than ( > ) the counter value. One pulse width is equal to tCLK × 65536.
Capture Mode
In capture mode, a signal edge that is detected at the T5CAP pin opens a gate and loads the current counter
value into the T5 data register. You can select the rising or falling edges to trigger this operation.
Timer 5 also gives you capture input source: the signal edge at the T5CAP pin. You select the capture input by
setting the value of the Timer 5 capture input selection bit in the port 3 control register low, P3CONL.1-.0
(3F003DH). When P3CONL.1-.0 is “00”, the T5CAP input is selected.
Both kinds of Timer 5 interrupts can be used in capture mode: the Timer 5 overflow interrupt is generated
whenever a counter overflow occurs; the Timer 5 match/capture interrupt is generated whenever the counter
value is loaded into the T5 data register.
By reading the captured data value in T5DATAH/L, and assuming a specific value for the Timer 5 clock
frequency, you can calculate the pulse width (duration) of the signal that is being input at the T5CAP pin.
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