S3CC40D/FC40D_UM_REV1.20
Calm16Core
SPECIAL REGISTERS
The special registers consist of 16-bit SR (Status Register), 22-bit PC (Program Counter), and saved registers for
IRQ (interrupt), FIQ (fast interrupt), and SWI (software interrupt). When IRQ interrupt occurs, the most significant
6 bits of the return address are saved in SPCH_IRQ, the least significant 16 bits of the return address are saved
in SPCL_IRQ, and the status register is saved in SSR_IRQ. When FIQ interrupt occurs, the most significant 6 bits
of the return address are saved in SPCH_FIQ, the least significant 16 bits of the return address are saved in
SPCL_FIQ, and the status register is saved in SSR_FIQ. When a SWI instruction is executed, the return address
is saved in A14 register (E14 concatenated with R14), and the status register is saved in SSR_SWI. The least
significant bit of PC, SPCL_IRQ and SPCL_FIQ is read only and its value is always 0.
— The 16-bit register SR has the following format.
15
8
7
0
T
–
–-
–
PM
Z1
Z0
V
TE
IE
FE
FE: FIQ enable bit, FIQ is enabled when FE is set.
IE: IRQ enable bit, IRQ is enabled when IE is set.
TE: TRQ enable bit, Trace is enabled when TE is set.
V: overflow flag, set/clear accordingly when arithmetic instructions are executed.
Z0: zero flag of R6, set when R6 equals zero and used as the branch condition when BNZD instruction with
R6 is executed.
Z1: zero flag of R7, set when R7 equals zero and used as the branch condition when BNZD instruction with
R7 is executed.
PM: privilege mode bit. PM = 1 for privilege mode and PM = 0 for user mode
T: true flag, set/clear as a result of an ALU operation.
FE, IE, TE, and PM bits can be modified only when PM = 1 (privilege mode). The only way to change from user
mode to privilege mode is via interrupts including SWI instructions. The reserved bit of SR (from bit 7 to bit 14)
can be used for other purposes without any notice. Hence programmers should not depend on the value of the
reserved bits in their programming. The reserved bits are read as 0 value.
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