S3CC40D/FC40D_UM_REV1.20
Calm16Core
INTERRUPTS
In CalmRISC16, there are five interrupts: RESET, FIQ, IRQ, TRQ, SWI. The RESET, FIQ, and IRQ interrupts
correspond to external requests. TRQ and SWI interrupts are initiated by an instruction (therefore, in a
deterministic way). The following table shows a summary of interrupts.
Name
Priority
Address
Description
RESET
1
000000h
Hardware Reset
FIQ
3
000002h
Fast Interrupt Request
IRQ
5
000004h
Interrupt Request
TRQ
2
000006h
Trace Request
SWI
4
000008h–0000feh
Software Interrupt
When nRESET (an input pin CalmRISC16 core) signal is released (transition from 0 to 1), “JMP addr:22” is
automatically executed by CalmRISC16. Among the 22-bit address addr:22, the most significant 6 bits are forced
to 0, and the least significant 16 bits are the contents of 000000h (i.e., reset vector address) of the program
memory. In other words, “JMP {6’h00, PM[000000h]}” instruction is forced to the pipeline. The initial value of PM
bit is 1 (that is, in privilege mode) and the initial values of other bits in SR register are 0. All other registers are not
initialized (i.e., unknown).
When nFIQ (an input pin CalmRISC16 core) signal is active (transition from 1 to 0), “JMP addr:22” instruction is
automatically executed by CalmRISC16. The address of FIQ interrupt service routine is in 000002h (i.e., FIQ
vector address) of the program memory (i.e., “JMP {6’h00, PM[000002h]}”). The return address is saved in
{SPCH_FIQ, SPCL_FIQ} register pair, and the SR value is saved in SSR_FIQ register. PM bit is set. FE, IE, and
TE bits are cleared. When RET_FIQ instruction is executed, SR value is restored from SSR_FIQ, and the return
address is restored into PC from {SPCH_FIQ, SPCL_FIQ}.
When nIRQ signal (an input pin CalmRISC16 core) is active (transition from 1 to 0), “JMP {6’h00, PM[000004h]}”
instruction is forced to the instruction pipeline. The return address is saved in {SPCH_IRQ, SPCL_IRQ} register
pair, and the SR value is saved in SSR_IRQ register. PM bit is set. IE and TE bits are cleared. When RET_IRQ
instruction is executed, SR value is restored from SSR_IRQ, and return address is restored to PC from
{SPCH_IRQ, SPCL_IRQ}.
When TE bit is set, TRQ interrupt happens and “JMP {6’h00, PM[000006h]}” instruction is executed right after
each instruction is executed. TRQ interrupt uses the saved registers of IRQ(that is, {SPCH_IRQ, SPCL_IRQ}
register pair and SSR_IRQ) to save the return address and SR, respectively. PM bit is set. IE, TE bits are cleared.
When “SWI imm:6” instruction is executed, the return address is saved in the register A14, and the value of SR is
saved in SSR_SWI. Then the program sequence jumps to the address (imm:6 * 4). PM bit is set. IE and TE bits
are cleared. “SWI 0” and “SWI 1” are prohibited because the addresses are reserved for other interrupts. When
RET_SWI instruction is executed, SR is restored from SSR_SWI, and the return address is restored to PC from
A14.
NOTES
1.
6’h00 is defined as 00 (or zero) in 6 bits
2.
imm:6 is defined as 6-bit immediate number
3-5