
S3CC40D/FC40D_UM_REV1.20
EXCEPTIONS
4
EXCEPTIONS
OVERVIEW
Exceptions in CalmRISC16 are listed in the table below. Exception handling routines, residing at the given
addresses in the table, are invoked when the corresponding exception occurs. The starting address of each
exception routine is specified by concatenating 0H (leading 4 bits of 0) and the 16-bit data in the exception vector
listed in the table. For example, the interrupt service routine for FIQ starts from 0H:PM[000002H]. Note that “:”
means concatenation and PM[*] stands for the 16-bit content at the address * of the program memory. When an
IRQ or FIQ occurs, current PC is pushed in the SPC_IRQ, SPC_FIQ on an exception. And if SWI is executed,
current PC is pushed in the E14:R14 register.
Table 4-1. Exceptions
Name
Address
Priority
Description
RESET
000000H
1st
Exception due to reset release.
FIQ
000002H
3rd
Exception due to nFIQ signal. Maskable by setting FE
IRQ
000004H
5th
Exception due to nIRQ signal. Maskable by setting IE
TRQ
000006H
2nd
Exception due to TE bit in SR register
SWI
000008H–
0000FEH
4th
Exception due to SWI execution
NOTE: Break mode due to BKREQ has a higher priority than all the exceptions above. That is, when BKREQ is active,
even the exception due to reset release is not executed.
HARDWARE RESET
When nRESET (an input pin CalmRISC16 core) signal is released (transition from 0 to 1), “JMP addr:22” is
automatically executed by CalmRISC16. Among the 22-bit address addr:22, the most significant 6 bits are forced
to 0, and the least significant 16 bits are the contents of
000000h (i.e., reset vector address) of the program
memory. In other words, “JMP {6’h00, PM[000000h]}” instruction is forced to the pipeline. The initial value of PM
bit is 1 (that is, in privilege mode) and the initial values of other bits in SR register are 0. All other registers are not
initialized (i.e., unknown).
4-1