INSTRUCTION SET
S3CC40D/FC40D_UM_REV1.20
PUSH Rn/PUSH Rn, Rm/PUSH An/ PUSH An, Am
The instruction “PUSH Rn” transfers 16-bit data from the register Rn to the memory location at the address of SP,
and then decrements the value of SP by 2. The register Rn should not be R15. The operation of “PUSH R15” is
undefined. The instruction “PUSH Rn, Rm” pushes Rn and then Rm. The registers Rn and Rm should not be the
same. The registers Rn and Rm should not be R15. The instruction “PUSH An” pushes Rn and then En. When
the extension register En is pushed, the value of En is zero-extended to 16-bit data. The register An should not be
A15. The instruction “PUSH An, Am” pushes An and then Am. The registers An and Am should not be the same
POP Rn/POP Rn, Rm/POP An/ POP An, Am
The instruction “POP Rn” increments the value of SP by 2, and then transfers 16-bit data to the register Rn from
the memory location at the address of SP. The register Rn should not be R15. The operation of “POP R15” is
undefined. The instruction “POP Rn, Rm” pops Rn and then Rm. The registers Rn and Rm should not be the
same. The registers Rn and Rm should not be R15. The instruction “POP An” pops En and then Rn. When the
extension register En is popped, the least significant 6 bits are transferred to En. The register An should not be
A15. The instruction “POP An, Am” pops An and then Am. The registers An and Am should not be the same
LDB Rn, @[Ai+disp:4] / LDB @[Ai+disp:4], Rn
The instructions transfer 8-bit data between the general register Rn and the memory location at the address of
(Ai+disp:4). disp:4 is a positive displacement from 0 to 15. The general register Rn is one R0 to R7. In the
instruction “LDB Rn, @[Ai+disp:4]”, the 8-bit data is zero-extended to 16-bit data, and then written into Rn. In the
instruction “LDB @[Ai+disp:8], Rn”, the least significant byte of Rn is transferred to the memory.
LDB Rn, @[Ai+disp:16] / LDB @[Ai+disp:16], Rn
The instructions transfer 8-bit data between the general register Rn and the memory location at the address of
(Ai+disp:16). disp:16 is a positive displacement from 0 to FFFFh. The general register Rn is one of R0 to R7. In
the instruction “LDB Rn, @[Ai+disp:16]”, the -bit data is zero-extended to 16-bit data, and then written into Rn. In
the instruction “LDB @[Ai+disp:16], Rn”, the least significant byte of Rn is transferred to the memory.
LDB R0, @[A8+disp:8] / LDB @[A8+disp:8], Rn
The instructions transfer 8-bit data between the general register R0 and the memory location at the address of
(A8+disp:8). disp:8 is a positive displacement from 0 to 255. In the instruction “LDB R0, @[A8+disp:8]”, the 8-bit
data is zero-extended to 16-bit data, and then written into R0. In the instruction “LDB @[A8+disp:8], R0”, the least
significant byte of R0 is transferred to the memory.
LDB Rn, @[Ai+Rj] / LDB @[Ai+Rj], Rn
The instructions transfer 8-bit data between the general register Rn and the memory location at the address of
(Ai+Rj). The value of Rj is zero-extended to 22-bit value. The general register Rn is one of the 8 registers from R0
to R7. In the instruction “LDB Rn, @[Ai+Rj]”, the 8-bit data is zero-extended to 16-bit data, and then written into
R0. In the instruction “LDB @[Ai+Rj], Rn”, the least significant byte of Rn is transferred to the memory.
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